Jordi Cosp

Synchronization of nonlinear electronic oscillators for neural computation

This paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, we study the microelectronic analog implementation of physical oscillators, instead of the software computer-simulated implementation. With this aim, the original oscillator has been adapted to a suitable microelectronic form. So as to study the hardware nonlinear oscillators, we propose two macro models, demonstrating that they preserve the synchronization properties. Secondary effects such as mismatch and output delay and their relation to network synchronization are analyzed and discussed. We show the correct operation of the proposed electronic oscillators with simulations and experimental results from a manufactured integrated test circuit. The proposed architecture is intended to perform the scene segmentation stage of an autonomous focal-plane self-contained visual processing system for artificial vision applications.

Scene segmentation using neuromorphic oscillatory networks

Using the neuromorphic approach, we propose an analog very large-scale integration (VLSI) implementation of an oscillatory segmentation algorithm based on local excitatory couplings and global inhibition. The original model has been simplified and adapted for its efficient VLSI implementation while preserving its segmentation properties. To demonstrate the feasibility of the approach, a 16/spl times/16-pixel testchip has been manufactured. Extensive experimental results demonstrate that it can properly segment binary images. Power consumption, segmentation time per cell, and system complexity are very low compared to other hardware and software implementation schemes. We also show two main differences between the original algorithm and the analog approach. First, the network is noise tolerant without the need of additional elements and second, delays between oscillators due to the combination of mismatch and output capacitances have to be accounted for network performance.

Implementation of compact VLSI FitzHugh-Nagumo neurons

In this paper we show a low power and very compact VLSI implementation of a FitzHugh-Nagumo neuron for large network implementations. The circuit consists of only 17 small transistors and two capacitors and consumes less than 23 muW. It is composed of a nonlinear resistor and a lossy active inductor. We demonstrate that a simple low Q active inductor can be used instead of a complex one because the parasitic series resistor can be easily embedded to the FitzHugh-Nagumo model. We also perform a statistical analysis to check the robustness of the circuit against mismatch.

A VLSI implementation of a neuromorphic network for scene segmentation

A VLSI implementation of a network of locally coupled oscillators for scene segmentation is presented. The circuit is based on LEGION (locally excitatory, globally inhibitory, oscillator network) algorithm and significant simplifications were made in order to reduce the silicon area overhead. We present the circuits for an analog VLSI implementation of the algorithm in a reduced area. The ability of the proposed implementation to segmentate simple images using oscillatory correlation is shown.

Design and basic blocks of a neuromorphic VLSI analogue vision system

Abstract In this paper we present a complete neuromorphic image processing system and we report the development of an integrated CMOS low-power circuit to test the feasibility of its different stages. The image system consists of different parallel-processing stages: phototransduction, non-linear filtering, oscillatory segmentation network and post-processing to extract fundamental characteristics. The circuit emulates some parts of the behaviour of biological neural networks as found in the retina and the visual cortex of living beings by adopting the neuromorphic approach that takes advantage of analogue VLSI electronics. The final objective is to develop a small and low-power system embedded in a single focal-plane integrated circuit suitable for portable applications. Each stage is briefly described. Simulations and experimental results of some basic blocks are also reported.

Field programmable switched capacitor voltage converter

In this paper we show two different schemes to implement a field programmable circuit that can connect n capacitors as a charge-pump of, eventually, any topology and switching pattern. Capacitor connectivity is configured by means of registers that control multiplexers that, in turn, select the phase signal that controls each switch. It is also shown that, with any of these schemes, dynamic configuration of the circuit may be achieved by simply adding additional control phases.

A low-voltage current sorting circuit based on 4-T min-max CMOS switch

A low-voltage, compact and fast circuit for sorting currents is reported. It is based on an enhanced four-transistor (4-T) min-max CMOS switch to reduce the switch voltage drop. The inherent avoidance of mirroring that produces mismatch is extended to the whole sorting circuit, while keeping the voltage drop to very low levels. The sorted output currents are by construction equal to the input currents, so errors can be greatly reduced compared to other approaches. Simulations show that, for a 0.35 µm technology, a three-stage cascade operates correctly at VDD = 1.2 V, being each stage voltage drop tens of mV.

Realistic model of compact VLSI FitzHugh–Nagumo oscillators

In this article, we present a compact analogue VLSI implementation of the FitzHugh–Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 μm double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design.

Selective similarity function for VLSI analog signal processing

The similarity calculation of two input voltages can be performed in the analog domain by means of a very compact current switch combined with a differential pair stage. Local feedforward of the current switch allows the circuit to work without the need of any external control ensuring at the same time very high selectivity. The current switch is analyzed by means of its large-signal model, since the first-order small-signal model is not enough to obtain insight into its behavior. The obtained peak cell circuit is applied to bioinspired gray-level image segmentation focal-plane processor. Other direct applications of the current switch are full-wave differential rectifiers and two-input maximum/minimum circuits.

A self-test and dynamics characterization circuit for MEMS electrostatic actuators

This paper presents a high-bandwidth capacitance estimation and driving circuit especially tailored for its use with MEMS electrostatic actuators. The circuit can be integrated as a part of a system comprising an electrostatic actuator to provide self-testing and failure prediction capabilities and also as a simple and low-cost actuator dynamics characterization system capable of measuring both periodic and non-periodic movements.