Jose Maiz

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

BTI reliability of 45 nm high-K + metal-gate process technology

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

Crystal plasticity in Cu damascene interconnect lines undergoing electromigration as revealed by synchrotron x-ray microdiffraction

Plastic deformation was observed in damascene Cu interconnect test structures during an in situ electromigration experiment and before the onset of visible microstructural damage (voiding, hillock formation). We show here, using a synchrotron technique of white beam x-ray microdiffraction, that the extent of this electromigration-induced plasticity is dependent on the linewidth. In wide lines, plastic deformation manifests itself as grain bending and the formation of subgrain structures, while only grain rotation is observed in the narrower lines. The deformation geometry leads us to conclude that dislocations introduced by plastic flow lie predominantly in the direction of electron flow and may provide additional easy paths for the transport of point defects. Since these findings occur long before any observable voids or hillocks are formed, they may have direct bearing on the final failure stages of electromigration.

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the V T variability at both time zero and after NBTI aging increases. The time0 V T variability can be explained by the random nature of dopants, whereas the randomly generated defects in the gate oxide can account for the aging-induced device DeltaV T variability. This paper focuses on the bias temperature instability stress-induced device DeltaV T variability and the trend across several technology generations. The remarkable correlation of aging-induced DeltaV T variability to the gate oxide area suggests that the continued device geometry scaling will increase the aging-induced variability. For the first time, aging-induced DeltaV T variability was characterized on transistors fabricated with high-kappa gate dielectric that also showed similar dependence to the gate oxide area.

Influence of phonon, geometry, impurity, and grain size on Copper line resistivity

The authors report on the resistivity of submicron copper lines ranging from 75to500nm linewidths as a function of temperature in the 10Kto380K interval. Their estimate of the contributions to electron scattering at 20K for the narrowest line (75nm linewidth) is 29% from copper surfaces, 25% from grain boundaries, and 30% from impurities, with the bulk resistivity making up the remaining 16%. It should be noted that at 300K, the contribution of electron-phonon scattering is about 60% illustrating the benefit of studying different scattering mechanisms at cryogenic temperatures.

Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents

The electromigration of Al-1%-Si interconnects under bidirectional (BC) and pulsed unidirectional (PDC) signals is discussed. The effect of signal asymmetry, duty cycle and frequency on the damage generation rate has been tested. The data suggests that the equivalent DC current of a non-DC signal is given by the average of the signal current for frequencies 1 kHz and higher. A transition region from an average DC equivalent circuit model to an ON-time equivalent type model has been identified around 1 Hz for PDC signals at 3.3E6 A/cm/sup 2/ and 200 degrees C. The refilling of microvoids under current reversal prevents the observation of that transition region for symmetrical bidirectional currents. PDC signals are shown to behave as particular cases of a generalized bidirectional signal. A physical model of the kinetics of material accumulation/depletion is described to show that a high-frequency operation approximation naturally leads to the average DC equivalent-current model. >

Isothermal stress relaxation in electroplated Cu films. I. Mass transport measurements

Recent studies on Cu interconnects have shown that interface diffusion between Cu and the cap layer dominates mass transport for electromigration. The kinetics of mass transport by interface diffusion strongly depends on the material and processing of the cap layer. In this series of two papers, we report in Part I the interface and grain-boundary mass transport measured from isothermal stress relaxation in electroplated Cu thin films with and without a passivation layer and in Part II a kinetic model developed to analyze the stress relaxation based on the coupling of grain boundary and interface diffusion. We show that a set of isothermal stress relaxation experiments together with appropriate modeling analysis can be used to evaluate the kinetics of interface and grain-boundary diffusion that correlate to electromigration reliability of Cu interconnects. Thermal stresses in electroplated Cu films with and without passivation, subjected to thermal cycling and isothermal annealing at selected temperatures...

In situ observations of dc and ac electromigration in passivated Al lines

In situ experiments have been carried out using a field emission scanning electron microscope (Hitachi S‐800) in order to characterize the dynamic behavior of electromigration (EM) voids under high spatial resolution. These experiments have shown how the EM voids move against the electron wind either in passivated or unpassivated lines under dc and low‐frequency ac currents.

Electromigration lifetime and critical void volume

We study electromigration in copper lines encapsulated in an organosilicate glass. A line fails when a void near the upstream via grows to a critical volume. We calculate the void volume as a function of time. The statistical distribution of the critical volume (DCV) is taken to be independent of testing variables, such as line length and electric current density. By contrast, the distribution of the lifetime (DLT) strongly depends on these testing variables. We deduce the DCV from the experimentally measured DLT. Once deduced, the DCV can predict the DLT under untested conditions.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.