Evan Grund

VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing

Very fast transmission line pulse (VF-TLP) systems described in the literature are time domain reflection (VF-TDR) configurations. Using other TLP configurations, VF-TLP systems can provide new capabilities. A wafer level Kelvin probe system was derived from VF-time domain transmission (VF-TDT). A test fixture board (TFB) using VF-time domain reflection and transmission (VF-TDRT) enables VF-TLP package level testing.

TLP systems with combined 50- and 500-/spl Omega/ impedance probes and Kelvin probes

Transmission line pulse (TLP) systems are mainly classified by their impedance, such as a 50- or 500-/spl Omega/ current source. A new TLP configuration allows switching between 50 and 500 /spl Omega/ by computer control to characterize a given part using both impedances. In addition, a four-needle Kelvin technique is introduced to TLP, which overcomes the measurement error from variations in contact resistance where the probe needles contact the wafer surface.

Empirical ESD simulation flow for ESD protection circuits based on snapback devices

This work describes an ESD empirical simulation flow for circuits containing snapback-based devices. Regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements. Behavioral language VerilogA code has been used to add measured characteristics of the transistor at triggering voltage dependent on simulated gate voltage.

Proper human body model testing of high voltage and “no connect” pins

“No Connect” pins were exempted from HBM testing due to tester delivery path parasitics producing an unintended CDM-like overstress. A modified two-pin HBM tester has been build that reduces overstressing to a level were valid testing of No Connect pins and high voltage pins with snapback protection is possible.

Practical HBM testing with statistical pin combinations

Instead of using a pin group approach as defined in the current HBM standard JS-001, stressing statistically determined pin pairs can drastically reduce the stress count and the stress time. The correlation of different HBM test methods is discussed with different examples, proving the wide applicability of this approach.