Josine Loo

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated

Single-cell recording and stimulation with a 16k micro-nail electrode array integrated on a 0.18 μm CMOS chip

To cope with the growing needs in research towards the understanding of cellular function and network dynamics, advanced micro-electrode arrays (MEAs) based on integrated complementary metal oxide semiconductor (CMOS) circuits have been increasingly reported. Although such arrays contain a large number of sensors for recording and/or stimulation, the size of the electrodes on these chips are often larger than a typical mammalian cell. Therefore, true single-cell recording and stimulation remains challenging. Single-cell resolution can be obtained by decreasing the size of the electrodes, which inherently increases the characteristic impedance and noise. Here, we present an array of 16,384 active sensors monolithically integrated on chip, realized in 0.18 μm CMOS technology for recording and stimulation of individual cells. Successful recording of electrical activity of cardiac cells with the chip, validated with intracellular whole-cell patch clamp recordings are presented, illustrating single-cell readout capability. Further, by applying a single-electrode stimulation protocol, we could pace individual cardiac cells, demonstrating single-cell addressability. This novel electrode array could help pave the way towards solving complex interactions of mammalian cellular networks.

Bottom-Up SiO2 Embedded Carbon Nanotube Electrodes with Superior Performance for Integration in Implantable Neural Microsystems

The reliable integration of carbon nanotube (CNT) electrodes in future neural probes requires a proper embedding of the CNTs to prevent damage and toxic contamination during fabrication and also to preserve their mechanical integrity during implantation. Here we describe a novel bottom-up embedding approach where the CNT microelectrodes are encased in SiO(2) and Parylene C with lithographically defined electrode openings. Vertically aligned CNTs are grown on microelectrode arrays using low-temperature plasma-enhanced chemical vapor deposition compatible with wafer-scale CMOS processing. Electrodes with 5, 10, and 25 μm diameter are realized. The CNT electrodes are characterized by electrochemical impedance spectroscopy and cyclic voltammetry and compared against cofabricated Pt and TiN electrodes. The superior performance of the CNTs in terms of impedance (≤4.8 ± 0.3 kΩ at 1 kHz) and charge-storage capacity (≥513.9 ± 61.6 mC/cm(2)) is attributed to an increased wettability caused by the removal of the SiO(2) embedding in buffered hydrofluoric acid. Infrared spectroscopy reveals an unaltered chemical fingerprint of the CNTs after fabrication. Impedance monitoring during biphasic current pulsing with increasing amplitudes provides clear evidence of the onset of gas evolution at CNT electrodes. Stimulation is accordingly considered safe for charge densities ≤40.7 mC/cm(2). In addition, prolonged stimulation with 5000 biphasic current pulses at 8.1, 40.7, and 81.5 mC/cm(2) increases the CNT electrode impedance at 1 kHz only by 5.5, 1.2, and 12.1%, respectively. Finally, insertion of CNT electrodes with and without embedding into rat brains demonstrates that embedded CNTs are mechanically more stable than non-embedded CNTs.

Low-Leakage Ultra-Scaled Junctions in MOS Devices; from Fundamentals to Improved Device Performance

Leakage currents in metal-oxide-semiconductor (MOS) devices are undesirable as they drain power supply resources in integrated circuits and systems. As MOS device dimensions scale, control of junction leakage and short channel effects (SCE) become more difficult. Scaling junctions can often trade-off drive versus SCE control and/or leakage. The 2005 edition of the ITRS roadmap states that an alternative architecture to bulk silicon is required for the 32 nm node and beyond. However, by intelligent junction scaling can we push bulk silicon beyond 45 nm onto 32 nm? Junction leakage generated by tunneling mechanisms becomes more significant as MOS technologies scale in bulk silicon. The four most common causes for this are (1) increased ultrashallow junction steepness, (2) increased channel and pocket concentrations, (3) increased junction curvature, and (4) reduced annealing thermal budget which promotes the presence of residual defects. In this work we quantify the contribution of these four key elements through a set of diode experiments. Electrical measurements were performed on fabricated diodes with different doping profiles, or with different levels of process induced damage. The key to, and novelty of, this experiment was that post-electricalcharacterization, the fabricated diodes were subjected to a deprocessing step where the contact metallization was removed, so that SIMS analysis could extract the doping profiles from the structures that were measured electrically before. The SIMS doping profiles were used as input in the device simulator MEDICI to enable a closer evaluation of the electrical measurements, to validate the accuracy of the physical models, and to address more device specific issues. We then investigated what junction methodologies are likely to fulfill the offstate leakage requirements for future generation MOS devices. Shown in Fig. 1 are SIMS depth profiles for 5 different n+/p diodes measured to extract the doping dependency of reverse bias leakage. The implant and anneal sequence is shown therein. The junctions were formed relatively deep, to avoid impact of surface effects from the metal strip, ensuring accurate SIMS analysis close to the junction. Fig. 2 shows the corresponding reverse bias current density as a function of voltage. As the background boron concentration increases, the current density also increases. It was determined by examination of the forward bias characteristics that the behavior of diodes in splits A and B was non-ideal (ideality factor n>>1), and were not included in the simulation methodology validation. Non-ideal behavior was also observed in p+/n diodes for high background concentrations of arsenic and phosphorus. For the ideal diodes of splits C, D, and E, the simulation results are quantitatively accurate for at least 8 orders of magnitude and reproduce the shapes of the measured curves very well. Finally in a set of MOS transistor experiments we demonstrate ultra-scaled low-leakage junctions suitable for future device scaling. Two approaches are shown schematically in Fig. 3, namely highly tilted implants and lowly-doped implants for MOS extensions. Improved device performance was illustrated in these experimental results even where processing was restricted to established approaches such as conventional ion implantation and spike anneal. By using only established processing techniques, these junction proposals are easy to integrate in a production environment.

Boron pocket and channel deactivation in nMOS transistors with SPER junctions

In this paper, we demonstrate the consequences of extension junction formation by low-temperature solid-phase-epitaxial-regrowth in nMOS transistors. Atomistic simulations, experimental device results, sheet resistance, and scanning spreading resistance microscopy data indicate that the high concentration of silicon interstitials associated with the end-of-range defect band promote the local formation of boron-interstitial clusters, and thus deactivate boron in the pocket and channel. These inactive clusters will dissolve after the high concentration silicon interstitial region of the end-of-range defect band has been annihilated. This nMOS requirement is in direct opposition to the pMOS case where avoidance of defect band dissolution is desired, to prevent deactivation of the high concentration boron extension profile.

Micro-sized syringes for single-cell fluidic access integrated on a micro-electrode array CMOS chip

Very-large scale integration and micro-machining have enabled the development of novel platforms for advanced and automated examination of cells and tissues in vitro. In this paper, we present a CMOS chip designed in a commercial 0.18 μm technology with integrated micro-syringes combined with micro-nail shaped electrodes and readout electronics. The micro-syringes could be individually addressed by a through-wafer micro-fluidic channel with an inner diameter of 1 μm. We demonstrated the functionality of the micro-fluidic access by diffusion of fluorescent species through the channels. Further, hippocampal neurons were cultured on top of an array of micro-syringes, and focused ion beam-scanning electron microscopy cross-sections revealed protrusion of the cells inside the channels, creating a strong interface between the membrane and the chip surface. This principle demonstrates a first step towards a novel type of automated in vitro platforms, allowing local delivery of substances to cells or advanced planar patch clamping.

Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

The new process module and device architecture options emerging for (sub-) 45nm CMOS lead to both opportunities and challenges for analog/RF circuit design. A survey is given describing the advanced process modules for competing architectures (planar bulk CMOS versus FinFETS), for different gate stacks and mobility enhancement techniques. Challenges for compact modeling are identified