Vaidy Subramanian

Planar Bulk MOSFET s Versus FinFETs: An Analog/RF Perspective

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage, excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, where the performance-power tradeoff is important. On the other hand, in high-frequency applications, planar bulk MOSFETs are seen to hold the advantage over FinFETs due to their higher peak transconductance. However, this comes at a cost of a reduced voltage gain of bulk MOSFETs

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated

Reliability Comparison of Triple-Gate Versus Planar SOI FETs

A comparative study of the reliability issues of triple-gate and planar FETs processed on the same silicon-on-insulator wafer is presented. It is shown that the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown (BD) for different gate voltages and temperatures. The apparent higher Weibull slope observed in planar devices with respect to the triple-gate devices is ascribed to the area dependence of the time-to-BD detection. In spite of the different surface orientations, low-frequency noise measurements indicate similar values of the interface trap density for triple-gate and planar FETs

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached at the same time. VT mismatch smaller than 3mV.µm is obtained for narrow (10nm) fins. Reduced speed sensitivity to gate pitch scaling and invertor delay reduced below 10 ps will be demonstrated.

Analysis of the FinFET parasitics for improved RF performances

FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in fT.

Characterization, modeling, and optimization of FinFET MOS varactors

For the first time, nMOS varactors fabricated in FinFET technology were characterized and modeled at microwave frequency. The RF analysis is carried out as a function of the fin width. It is shown that the fin width has nearly no impact on the tuning range of the device, but on the quality factor (Q). Best Qs are obtained for wide fin devices, mainly due to the reduction of the series resistances, and a higher intrinsic conductance

Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges

The new process module and device architecture options emerging for (sub-) 45nm CMOS, lead to both opportunities and challenges for analog/RF circuit design. These will be discussed both at the device level and circuit level for two competing architectures (planar bulk CMOS versus FinFETs), for different gate stacks and mobility enhancement techniques. Very high cutoff frequencies will be demonstrated for planar bulk CMOS devices, while FinFETs exhibit high voltage gain and excellent matching performance. As a result, FinFETs will be shown to be better suited for analog baseband design and to have acceptable RF performance in the 1-10 GHz range, while planar bulk CMOS outperforms the FinFETs for sub-circuits above 10 GHz

Perspectives of (sub-) 32nm CMOS for Analog/RF and mm-wave Applications

New process modules and device architectures for (sub-) 32 nm CMOS lead to both opportunities and challenges for analog/RF and mm-wave circuit design. A survey will be given describing the advanced process modules and competing architectures (planar bulk CMOS versus FinFETS), and their impact on analog/RF performance. FinFETs will be shown to be better suited for analog baseband design and to have acceptable RF performance in the 1-10 GHz range, while planar bulk CMOS outperforms the FinFETs for sub-circuits above 10 GHz.

Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS

We report for the first time a comprehensive comparison of the intra-die matching performance of most advanced multiple gate (MuGFETs) and planar bulk MOSFET technologies in terms of architectures and process modules like the gate stack and source/drain engineering. The impact of Ni-based fully silicided (FUSI) and metal (TiN and TaN) gates for bulk devices, selective epitaxial growth (SEG) and thickness of the Ni salicidation layer for MuGFETs on both threshold voltage (VT) and current factor (beta) mismatch is investigated. Taking into account the device DC and matching performances, our measurements show that FUSI planar devices and MuGFETs combining selective epitaxial growth (SEG) and thin Ni salicidation are interesting candidates for applications at the 45 nm node and beyond, with VT mismatch of 3.1 and 2.3 mV.mum for n-type devices, respectively.

Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

The new process module and device architecture options emerging for (sub-) 45nm CMOS lead to both opportunities and challenges for analog/RF circuit design. A survey is given describing the advanced process modules for competing architectures (planar bulk CMOS versus FinFETS), for different gate stacks and mobility enhancement techniques. Challenges for compact modeling are identified