Jozef Mitros

16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology

In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set, photo aligned, coimplanted double-diffused well (DWL), (2) two n-type dopings in the drift region, and (3) shrink from 1.0 /spl mu/m to 0.72 /spl mu/m. The R/sub sp/ vs. BV/sub dss/ trend for these devices is the best reported to date for conventional lateral technology: @V/sub gs/=12.75 V (3 MV/cm) R/sub sp/=0.95 m/spl Omega/ cm/sup 2/, BV=69.3 V; R/sub sp/=0.68 m/spl Omega/ cm/sup 2/, BV=50.0 V; R/sub sp/=0.45 m/spl Omega/ cm/sup 2/, BV=33.0 V; R/sub sp/=0.36 m/spl Omega/ cm/sup 2/, BV=19.0 V; for 60, 40, 25, and 16 V rated conventional LDMOS devices.

A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V

This work presents a new reduced-surface-drain (RSD) type of LDMOS in comparison with very thin RESURF (VTR) and conventional (CONV) devices for 20 V BiCMOS market applications. Competitive performance results obtained for the RSD, VTR and CONV devices are respectively R/sub sp/=0.39 m/spl Omega//spl middot/cm/sup 2/ BV=24.4 V; R/sub sp/=0.30 mn/spl Omega//spl middot/cm/sup 2/, BV=25 V; R/sub sp/=0.59 m/spl Omega//spl middot/cm/sup 2/, BV=18-20 V. All R/sub sp/, measurements are with 3 MV/cm gate stress(V/sub gs/=12.75 V, Tox=425 /spl Aring/).

High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design

This paper describes the integration of the 20V complementary drain-extended MOS (DECMOS) and fully isolated drain-extended NMOS (DENMOS) transistors into a high-volume 0.13mum CMOS technology with two additional masks. The 20V devices were optimized for Rsp-BVdss performance without compromising the advanced 1.5V CMOS performance in the 0.35mum pitch copper, low-K dielectric process flow. This cost-effective process is very competitive for the power management (PM) chip design of portable devices

Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process

The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R/sub sp/) at the 20 V node. The 20 V rated lateral power device is difficult to optimize because modern VLSI processes tend to physically limit surface BV to about 13-19 V in planar devices. Here the structure performance is advanced by optimizing a Very-Thin-RESURF (VTR) region (VTR Xj=0.3 /spl mu/m). This work presents a planar VTR drain extended IGFET with best case BV=25 V and R/sub sp/=0.34 m/spl Omega//spl middot/cm/sup 2/@V/sub gs/=10 V using a compressed BiCMOS VLSI, 1 /spl mu/m technology. Structure variation and thermal performance are characterized.