Judy Wang

Producer BARC open challenges and the baseline set up for FinFET

Multiple Vt tuning is necessary for SOC (system-on-a-chip) FinFET devices at 16nm technology node and beyond. To achieve this, BARC open, as a mask, for NMOS/PMOS implantation process is needed. Vertical profile with enough PR effective height is the key challenge of this process. Besides, WPH for run cost reduction is another major consideration from customer perspective. So gas N2/NH3 chemistry is adopted for its high etch rate, and thus high throughput. For this recipe to get a good etch uniformity on blanket wafer first to ensure good performance on the whole pattern wafer, each parameter was studied, that is, bias power, pressure, NH3 flow, N2 low, FRC, gap, and backside helium pressure. Finally, etch rate >1000A/min with good uniformity <4% on blanket BARC wafer was got using optimized bias power and gap. Results on pattern wafer show performance is almost acceptable, it is near to vertical and PR effective height is enough.

Control of Contact Hole Distortion by Using Polymer Deposition Process (PDP) for sub-65nm Technology and Beyond

Contact hole distortion in dielectric etching was investigated and it is found that the contact hole distortion is mainly caused by low mask selectivity, poor mask surface control (roughness, striation, pitting or pin hole) before and after etching. The surface roughness and mask selectivity have been studied to overcome the problem of pattern deformation of photoresist (PR) and C-rich materials as the mask. By using the polymer deposition process (PDP), the mask degradation is improved and the contact profile is well controlled. This paper focuses on the discussion of PDP chemistry selection, PDP time decision, and PDP used at before or after BARC (bottom anti-reflective coating) open step