Juergen Faul

Low-variation SRAM bitcells in 22nm FDSOI technology

We present the SRAM bitcell offering from 22FDX^TM (a 22nm FDSOI technology) with competitive 1.46mV-µm FinFET-like transistor mismatch coefficient (AVt) built with low cost planar architecture. Extremely low minimum operating voltages (V<inf>min</inf>) are reported for both the high-density (HD) 0.110μm² and high-current (HC) 0.124μm² bitcells without any assist, showing 95% limited yield (LY) Vmin values of 0.6V and 0.5 V for 64Mb HD and 128Mb HC arrays, respectively. Due to FDSOI architecture, bitline capacitance (Cbl) of the HD 0.110um² bitcell is similar to 14nm FinFET Hd 0.064um² bitcell, and more than 30% lower compared to 28nm high-k metal gate (HKMG) HD 0.127um² bitcell. Finally, we tune SRAM performance and stability with the use of back-gate bias to demonstrate HD standby leakage of 5pA/cell and two-port (TP) 0.185 μm² assisted 64Mb 95% LY V<inf>min</inf> of 0.44 V.