Peter Javorka

Transistor With Embedded Si/Ge Material Having Reduced Offset and Superior Uniformity

Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material

SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING A LAYER OF A STRESS-CREATING MATERIAL AND METHOD FOR THE FORMATION THEREOF

Method of Increasing the Germanium Concentration in a Silicon-Germanium Layer and Semiconductor Device Comprising Same

A SEMICONDUCTOR DEVICE HAVING STRESSED ETCH STOP LAYERS OF DIFFERENT INTRINSIC STRESS IN COMBINATION WITH PN JUNCTIONS OF DIFFERENT DESIGN IN DIFFERENT DEVICE REGIONS

Methods for fabricating semiconductor devices

Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation

SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN

PMOS Threshold Voltage Control by Germanium Implantation

Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth