Jun-sik Oh

Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90 nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 108 cycles, respectively. In addition, they are non-destructively readable above 107 read pulses at 100 ns and 1 uA.

Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge2Sb2Te5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

43.3: Power Efficient AMOLED Display with Novel Four Sub-Pixel Architecture and Driving Scheme

We present a novel all-phosphorescent AMOLED pixel architecture with a red, green, light blue and deep blue sub-pixel design. The highly efficient light blue reduces power consumption by 33% compared to an equivalent conventional RGB display using a fluorescent blue sub-pixel. Furthermore, by using a light and deep blue sub-pixel layout, the lifetime of the display will be significantly increased due to the reduced on-time required for the deep blue sub-pixel. Here we demonstrate this new design in a 2.5-inch AMOLED panel.

Field assisted spin switching in magnetic random access memory

A switching method called by field assisted spin switching has been investigated. A field assisted spin switching consists of a metal line induced magnetic field and a spin switching through a magnetic tunnel junction. It is a variation of a current induced switching and assisted by the magnetic field induced by the current-carrying metal line. Various current paths have been tested to investigate how and how much the spin switching contributes to the overall switching and the results will be explained. A computer simulation has been complemented to measure the degree of the thermal effect in the switching.

A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due to insufficient cell capacitance. It is widely accepted that the MIM capacitor using high dielectric constant material is inevitable for 0.15 /spl mu/m technology and beyond. Although many studies to use high dielectric material have been reported, those studies are not adequate for 0.15 /spl mu/m technology and beyond because most of the studies are either based on a simple capacitor module process or based on large feature size design rules. In this paper, for the first time, a DRAM technology using BaSrTiO/sub 3/ (BST) MIM capacitors is developed with 0.15 /spl mu/m technology.

Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of Al/TiO 2 based Resistive Switching Memory and its Mechanism for MLC Operation

1 Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea 2 DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San 16, Banwol-dong, Hwasung-city, Gyeonggi-do 445-701, Republic of Korea Tel.: +82-2-880-7279, Fax: +82-2-882-4658, E-mail address: grayeyez@snu.ac.kr

Full Integration of Highly Reliable Phase Change Memory With Advanced Ring Type Bottom Electrode Contact

ABSTRACT We successfully developed 256Mb Phase Change Random Access Memory (PRAM) based on 0.10μ m-CMOS technologies using ring type contact. The writing current with uniform CD process variation of Bottom Electrode Contact (BEC) was achieved by improving CMP process and developing core dielectric material. Also, the ring type contact scheme provided strong reliability such as the cycling endurance and data retention time for 256 Mb high density PRAM.

An 8F/sup 2/ MRAM technology using modified metal lines

A novel 8F/sup 2/ cell structure for high density magnetic random access memory (MRAM) and its operating characteristics are proposed. In this new scheme, we formed bottom electrode contact (BEC) through twin metal lines (MLs) and a magnetic tunnel junction (MTJ) was located just on the BEC for the reduction of cell size. From the results of simulation and experiment, we have confirmed that the generated magnetic field in the new scheme is more uniform than that in the conventional scheme with a negligible reduction of writing field strength. We adopted a self-aligned BEC process to prevent electrical shorting between ML and BEC. To avoid electrical shorting and improve the magnetic properties of MTJs, a chemical mechanical polishing (CMP) process was adopted before MTJ deposition. As a result, we confirmed the feasibility of high-density 1T1MTJ MRAM, composed of 8F/sup 2/ cells with optimal MTJ characteristics.

Areal and Structural Effect on Oxide based RRAM cell for Improving Resistive Switching Characteristics

1 Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea 2 New Memory Lab, R&D Division and 3 Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., Nongseo-dong, Giheung-gu, Yongin-si, Gyeonggi-Do, Korea, 445-701 Tel: +82-2-880-7279, Fax: +82-2-882-4658, E-mail address: kiyan42@snu.ac.kr