Jun-Won Lee

The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90 nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 108 cycles, respectively. In addition, they are non-destructively readable above 107 read pulses at 100 ns and 1 uA.

MLC PRAM with SLC write-speed and robust read scheme

We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

Novel flowable CVD process technology for sub-20nm interlayer dielectrics

Flowable CVD (Chemical Vapor Deposition) process having merits in terms of both superior gap-fill performance of SOD (Spin-on Dielectric) and process stability of CVD was introduced for the interlayer dielectric (ILD) in sub-20nm devices based on new concept and precursor. Remote plasma during low temperature deposition and ozone treatment was adopted to stabilize the film. We also developed a novel Flowable CVD process which does not oxidize Si or electrode, resulted in removal of Si3N4 stopper layer as an oxidation or diffusion barrier. After the application of Flowable CVD to 20nm DRAM ILD, we could reduce not only loading capacitance of Bit-line by 15% but also enhance comparable productivity. Through the successful development of sub-20nm DRAM ILD Gap-fill process, Flowable CVD was successful demonstrated as a promising candidate for mass production-worthy ILD in sub-20nm next generation devices.

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

Robust spin-on glass gap-fill process technology for sub-30nm interlayer dielectrics

A highly robust gap-fill process technology of spin-on glass (SOG) was developed for the interlayer dielectric (ILD) in sub-30nm devices. We revealed that the filling behavior of SOG within gaps during spin-coating is mainly dependent on the capillary effect. The highly wettable surface treatment prior to SOG coating was found to enhance the gap-fill performance remarkably. This technique plays a key role in maximizing capillary effect by raising surface wettability. The filling capability was also improved by optimization of baking temperature to minimize the viscosity of SOG. It was finally found that the defects of contact bridges due to poor filling of SOG were reduced to be almost free by those unique process refinements.

Low-current Spin Transfer Torque MRAM

To achieve low write current in high density Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) arrays, it is important to understand and co-optimize the different kinds of device switching currents, governed by different materials parameters. We demonstrate that double magnetic tunnel junctions (DMTJs) lower the switching current threshold Ic0 by a factor of two when compared to conventional single MTJs. In single MTJs, the overdrive required to reach a write-error rate (WER) of 1E-6 was reduced by materials optimization from 53% to 29% a write-error rate (WER) of 1E-6 by materials optimization. Ultra-low switching current of 8 µA at WER = 1E-9 was achieved in an 11 nm MTJ with 10 ns write pulses.

Fabrication of small contact with novel mask design

Using novel mask design, it was possible to print 0.28 /spl mu/m contacts with i-line lithography and 0.22 /spl mu/m contacts with DUV lithography. With a higher NA DUV stepper, it will be possible to print even smaller contacts for 1 Gbit DRAMs.