Chilhee Chung

High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications

A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.

MLC PRAM with SLC write-speed and robust read scheme

We have proposed an integrated method to realize MLC PRAM at 45nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.

Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved by the appropriate offset which reduces the leakage current through the select transistor. It is proved that the TCAT NAND is a manufacturable technology in terms of reliability as well as performance in a channel hole with a diameter of 90nm.

A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.

Highly manufacturable silicon vertical diode switches for new memories using selective epitaxial growth with batch-type equipment

Practical selectivity window of selective epitaxial growth (SEG) using a H2/SiH4/Cl2 cyclic chemical vapor deposition (CVD) system has been investigated with the batch-type vertical furnace equipment, replacing a conventional single-wafer H2/dichlorosilane/HCl CVD system. The process temperature was less than 700 °C, which is suitable for a low thermal budget process applicable to next-generation memories including vertical pn-diode switches. Selectivity loss is quantified by an in-line inspection tool to determine the practical number of selectivity losses. The H2/SiH4/Cl2 cyclic CVD system provides an excellent capacity of 40 wafers per batch. Selectivity loss, which is one of the most crucial features in the SEG process for the diode application, is controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and the practical number of selectivity loss is confirmed to be less than 100 in 200 mm wafers. Without high temperature annealing in hydrogen ambient, low temperature cyclic SEG in the batch reactor ensures the clean interface and improved crystalline quality of SEG-Si, as well as high throughput.

New phenomena for the Lifetime Prediction of TANOS-based Charge Trap NAND Flash Memory

Through the evaluation and analysis of the data retention characteristics, it was found that the CTF memory cell behaviors are quite different from conventional that of the FG type flash memory cell in terms of Arrhenius plot of data retention because Ea of the CTF memory cell has a high dependency on the bake temperature and P/E cycles. A proper acceleration test condition is needed to predict the data retention lifetime of the CTF memory, considering the change of Ea in the low temperature region (<125°C).

Both NOR and NAND Embedded Hybrid Flash for S-SIM Application Using 90 nm Process Technology

We have firstly demonstrated a hybrid flash including both NOR and NAND cell in a single chip using 90 nm logic technology for S-SIM (Super-Subscriber Identity Module) application. The memory sizes are 16 MB NAND and 768 kB NOR flash, respectively. The flash memory cells exhibited over 10 k-cycle endurance and 10-year retention for the successful smart card application.

A comprehensive study of degradation behavior of select transistors in the Charge Trap Flash memories

The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.