Dae-Won Ha

Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90 nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 108 cycles, respectively. In addition, they are non-destructively readable above 107 read pulses at 100 ns and 1 uA.

Recent Advances in High Density Phase Change Memory (PRAM)

Phase-change Random Access Memory (PRAM) has drawn much attention as a promising candidate for the next generation nonvolatile memory. This is because PRAM has a great potential not only to provide adequate solutions for solving the scaling issues that other conventional nonvolatile memories might face in near future, but also to create new functions and applications of its own with its fast write programming speed and direct overwrite capability. As a result, PRAM has been the fastest evolutionary memory and it is close to commercialization. In this paper, recent progresses in PRAM technologies will be discussed and future direction will be proposed.

Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge2Sb2Te5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 /spl mu/m technology node and beyond

In this paper, a 0.15 /spl mu/m embedded DRAM technology is described which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-function gate with Si/sub 3/N/sub 4/ capped Ti polycide, and selective Co silicidation of source/drain diffusion by Si/sub 3/N/sub 4/ liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-aligned contact (SAC) etching. Low temperature Al/sub 2/O/sub 3/ stacked cell capacitor with hemispherical grain (HSG) makes it possible to realize the sufficient storage capacitance in DRAM arrays and the high performance transistor. The CMP planarization of interlayer dielectric enlarges the depth of focus for lithography and enables the multilevel metallization. These integration technologies can be fairly extendible to the future embedded DRAM in 0.13 /spl mu/m technology node and beyond.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

Active Width Modulation (AWM) for cost-effective and highly reliable PRAM

This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔIPGM, is reduced from 17.8% to 0.82%, and that of a write energy, ΔEPGM, from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, IRESET, for sub-40 nm PRAM technology and so on.