Jung-Hyeon Lee

Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates

This paper reports on new concept consisting of all-oxide-based device component for future high density non-volatile data storage with stackable structure. We demonstrate a GaInZnO (GIZO) thin film transistors (TFTs) integrated with 1D (CuO/InZnO)-1R (NiO) (one diode-one resistor) structure oxide memory node element. RRAM (Resistance Random Access Memory) has provided advantages in fabrication which have made these works possible. Therefore we also suggest methods and techniques for improving the distribution in bi-stable resistance characteristics of the NiO memory node. In order to fabricate stack structures, all device fabrication steps must be possible at low temperatures. The benefits provided by low temperature processes are demonstrated by our devices fabricated over glass substrates. Our paper shows the device characteristics of each individual component as well as the characteristics of combined select transistor with 1D-1R cell. XPS analysis of NiO RRAM resistance layer deposited by ALD confirms similar conclusions to previous reports of the importance of metallic Ni content in sputtered NiO for bistable resistance switching. Also we herein propose a generalized stacked-memory structure to minimize on-chip real estate to maximize integrated density.

Comparative structural and electrical analysis of NiO and Ti doped NiO as materials for resistance random access memory

In order to investigate the mechanism behind bistable resistance switching in NiO thin films, we have done detailed x-ray photon spectroscopy (XPS) and x-ray diffraction Analysis (XRD) on NiO and Ti doped NiO samples fabricated under various conditions. We discovered that a high initial resistivity was required for samples to undergo bistable resistance switching, and the presence of metallic Ni content in these samples was determined by XPS. XRD data also showed that NiO grown with a relative (200) orientation was preferred over those grown with relative (111) orientation.

Weak-microcavity organic light-emitting diodes with improved light out-coupling

We propose and demonstrate weak-microcavity organic light-emitting diode (OLED) displays with improved light-extraction and viewing-angle characteristics. A single pair of low- and high-index layers is inserted between indium tin oxide (ITO) and a glass substrate. The electroluminescent (EL) efficiencies of discrete red, green, and blue weak-microcavity OLEDs are enhanced by 56%, 107%, and 26%, respectively, with improved color purity. Moreover, full-color passive-matrix bottom-emitting OLED displays are fabricated by employing low-index layers of two thicknesses. As a display, the EL efficiency of white color was 27% higher than that of a conventional OLED display.

Formation of plasma induced surface damage in silica glass etching for optical waveguides

Ge, B, P-doped silica glass films are widely used as optical waveguides because of their low losses and inherent compatibility with silica optical fibers. These films were etched by ICP (inductively coupled plasma) with chrome etch masks, which were patterned by reactive ion etching (RIE) using chlorine-based gases. In some cases, the etched surfaces of silica glass were very rough (root-mean square roughness greater than 100 nm) and we call this phenomenon plasma induced surface damage (PISD). Rough surface cannot be used as a platform for hybrid integration because of difficulty in alignment and bonding of active devices. PISD reduces the etch rate of glass and it is very difficult to remove residues on a rough surface. The objective of this study is to elucidate the mechanism of PISD formation. To achieve this goal, PISD formation during different etching conditions of chrome etch mask and silica glass was investigated. In most cases, PISD sources are formed on a glass surface after chrome etching, and...

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

STT-MRAM with double magnetic tunnel junctions

We report switching performance of perpendicularly magnetized Spin-Transfer Torque MRAM (STT-MRAM) devices with double tunnel barriers and two reference layers. We show that stacks with double tunnel barriers improve the switching efficiency (Eb/Ic0) by 2x, when compared to similar stacks with a single tunnel barrier. Switching efficiency up to 10 kBT/uA was observed in single devices. A large operating window, Vbreakdown-Vclons ~ 0.7 V was achieved for 40nm devices, compared to 0.2V in single tunnel barrier devices.

Uniformity measurement of electron emission from carbon nanotubes using electron-beam resist

The field-emission sites’ distribution was measured to monitor the emission uniformity from randomly oriented carbon-nanotube (CNT) emitters using electron-beam resists (ER). The dot-patterned CNT emitters were fabricated by screen-printing a photoimageable CNT paste on an indium doped tin oxide (ITO) coated glass plate. An ER-coated Si substrate used as an anode provides the detection of the location and amount of the electron emission from the partial number of active emission sites among many existing CNTs. The measurements were carried out with the variation of electrical fields through continuous- or pulsed-voltage applications on a diode-type configuration. Developed ER images after a similar dosage of field-emission current flow indicate that emission uniformity is improved as the electrical field is increased. This method suggests that the emission uniformity could be estimated for various conditions of emitter preparation, such as CNT type, paste composition, and dispersion process, as well as th...

Fabrication of Cu/Co bilayer gate electrodes using selective chemical vapor deposition and soft lithographic patterning

A templated Cu/Co bilayer gate electrode was fabricated using the combined method of consecutive and selective chemical vapor deposition (CVD), and octadecyltrichlorosilane (OTS) microcontact printing techniques. Soft lithographically patterned self-assembled monolayers (SAMs) can direct the growth of Co occurring at the low temperatures 50–90 °C and serve as a template for the consecutive and selective growth of Cu, thereby forming stable and high quality Cu/Co bilayer gate electrodes on a glass substrate. This simple process provides fewer process steps and higher performance than other conventional processes, and can be applied to the fabrication of large area and high resolution thin film transistor liquid crystal displays.

Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement

In order to control the on-chip linewidth variation (OCV) in logic devices, accurate optical proximity correction (OPC) is required, and the method to enhance its result is devised. The optical proximity behaviors are severely varied according to the optical and material conditions. The change in photoresist (PR) species deteriorates the OPC rule from 9.3 nm to 15.1 nm for two kinds of PR species. The illumination condition variation also deteriorates the optical-proximity-corrected (OPCed) results from 9.3 nm to 11.6 nm. To obtain accurate OPCed results, these conditions should be fixed. For improving the correction accuracy of the optical proximity, the OPCed grid size effect on the critical dimension (CD) uniformity is evaluated quantitatively. By adopting the OPC grid size of less than 1 nm, the correction resolution limited by the grid size is enhanced. The selective bias with the assist features is applied to the line-and-space (L/S) patterns varied by the space sizes. The selective bias rule is generated with a model using the different grid sizes of 1 nm and 0.5 nm. In the nominal CD of 87 nm, the 3σ values of the optical proximity effect are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The improvement of 9.2 nm is achieved, corresponding to nearly 39% enhancement. The CD uniformity dependence on the grid size was characterized in two-dimensional pattern on a real static random access memory (SRAM) pattern with the different grid sizes of 1 nm and 0.5 nm. The 3σ values of the uniformity are 9.9 nm and 8.7 nm in the case of grid sizes of 1 nm and 0.5 nm, respectively. Decreasing the grid size improves the uniformity by 4.7 nm, corresponding to 22% enhancement. By considering the mask error enhancement factor (MEEF), the enhanced amount is calculated to be 3.2 nm. The pattern fidelity improvement in the mask by reducing the grid size enhances the printing images, and decreases the measurement error using the in-line CD scanning electron microscope (SEM).