Joon-soo Park

Optimization of Sample Plan for Overlay and Alignment Accuracy Improvement

The overlay control requirement for a sub-0.15 µm design rule device is nominally less than 40 nm. To meet this demand, every factor known to affect the overlay budget should be analyzed in detail and corrected as much as possible. One of the major causes degrading the overlay budget is the nonoptimized wafer sample plan. Compensated but undercorrected overlay errors fitted as linear terms can be amplified in case of using improper sample plan (e.g., an asymmetric plan). In this study, we investigated the sample plan dependency of global alignment repeatability and overlay measurement accuracy. The achievement of better alignment repeatability is critical for improving not only in-wafer overlay but wafer-to-wafer overlay control. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected for global alignment use. Several sample plans which are limited to the symmetric group (i.e., translation, inversion, rotation and symmetric), are tested. The criteria for selecting the optimum sample plan were the residuals and linear-term reproducibility, both of which are significantly affected by raw data noise. Raw data variations include stage positioning errors and process-induced alignment signal abnormality. From among the candidates, we determined an optimal sample plan which leaves the least residuals and exhibits repeatability as good as that in full chip measurement. Similar results could be obtained for an overlay sample plan.

Monte Carlo simulation study of local critical dimension error on mask and wafer

Summary form only given. Mask Error Enhanced Factor (MEEF) is the important issue in sub-100 nm lithography. In addition, the types of patterns written on the mask become so complicated that the variation of critical dimension (CD) on mask can be crucial for determination of wafer CD uniformity. The CD variation on mask consists of two components, local and global CD variation. These are the two main sources inducing the CD variation on a wafer. The printed image on wafer can be distorted due to proximity effect caused by near neighboring features on mask. Therefore, MEEF simulation and local CD error calculation should be performed with careful consideration for the effect caused by near neighboring features. The Monte Carlo method has been applied to images printed on wafer in order to evaluate the effects mentioned above.

Challenge to 0.13-μm device patterning using KrF

The extension of optical lithography to sub-0.18micrometers design rule using high NA KrF lithographic tool and resolution enhancement technique (RET) is strongly required because of the delayed ArF lithography technology. The theoretical limits, i.e., the diffraction limits of KrF lithography show that 0.1(Mu) m is in the unreachable region with current exposing tool of 0.6NA and even with high NA KrF scanners which will be available soon. Therefore 0.13micrometers device with 0.26micrometers pitch will be a real challenge to most lithographers. In this paper we discuss the status of 0.13micrometers device and show some of the critical device patterns exposed with several KrF scanners which are currently available. Many problems can easily be predicted and must be overcome. The challenge, however, seems to be surmountable in the near future.

Free energy modeling of block-copolymer within pillar confinements on DSA lithography

To a major candidate and beyond, directed self-assembly (DSA) lithography is investigated on DRAM contact-hole fabrication. We perform a systematic study about behavior of asymmetric PS-b-PMMA block copolymers (BCP) within pillar confinement for DSA and find that selectively removed PMMA contact domain has a different morphology according to chemically modified pillar surfaces. We calculate the perturbation of PMMA contacts by pillar diameter using free energy magnitude model. This established model provides practical engineering insight for present pillar scheme and future graphoepitaxial self-assembly techniques for semiconductor DSA procedure.

The use of computational inspection to identify process window limiting hotspots and predict sub-15nm defects with high capture rate

As critical dimensions for advanced two dimensional (2D) DUV patterning continue to shrink, the exact process window becomes increasingly difficult to determine. The defect size criteria shrink with the patterning critical dimensions and are well below the resolution of current optical inspection tools. As a result, it is more challenging for traditional bright field inspection tools to accurately discover the hotspots that define the process window. In this study, we use a novel computational inspection method to identify the depth-of-focus limiting features of a 10 nm node mask with 2D metal structures (single exposure) and compare the results to those obtained with a traditional process windows qualification (PWQ) method based on utilizing a focus modulated wafer and bright field inspection (BFI) to detect hotspot defects. The method is extended to litho-etch litho-etch (LELE) on a different test vehicle to show that overlay related bridging hotspots also can be identified.

CD budget analysis on sub-50-nm DRAM device: global CD variation to local CD variation

In this study, overall critical dimension (CD) error budget analysis procedure is proposed to estimate the source of CD error. Until now, local CD variation has been treated as noise or uncertainty, since it has been considered not real, and it is difficult to be measured. However, the actual measurement result shows the local CD variation occupies a significant portion of overall CD variation. We included the local variation into overall CD budget analysis, and performed the budget break-down of the local CD variation. This analysis was performed on the layers of a sub-50nm DRAM device. We calculated local CD uniformity from CD SEM measurement data having multi-point measurement on each frame. Metrology error of wafer CD SEM and mask CD SEM was measured, and local CD uniformity (CDU) of mask was also measured. To estimate the impact from the mask local CDU, we performed simulation with a virtual mask shape which has the same level of local variation with real mask. The remaining budget, except metrology and mask induced budget, is treated as a process roughness. To predict the budget caused by process roughness, a randomly varying threshold map was applied. In this approach, the local CD variation of 2-dimensional patterns is considered as an extension of the LWR in 1-dimension.

Era of double exposure in 70 nm node DRAM cell

In this paper, two different methods of double exposure are proposed to improve the resolution in low k1 lithography. One is using an additional mask to complement the lack of image contrast. The other is to fix the mask and only use combinations of illumination systems to increase image contrast. By applying image assisting double exposure to asymmetry dense contact under k1=0.33, the process window can be doubled in comparison to the single exposure method. By an appropriate design of two masks, we could also minimize the image distortion from overlay shift by mixture of masks. Effective first order efficiency is defined as a new term in double exposure with complementary illumination. The larger the value is, the better the image contrast becomes. Through an experiment and simulation in k1=0.30, in double exposure with two illuminations and the same mask, that wider process window was obtained than in single exposure with optimized illumination system, and also 0.10um of DOF (Depth of Focus) was obtained under k1=0.28.

ArF issues of 90-nm-node DRAM device integration

Recently, the design rule shrinkage of DRAM devices has been accelerated. According to International Technology Roadmap for Semiconductor (ITRS) 2001, 90 nm node will start in 2004. For this achievement, lithography has been standing especially in the forefront and leading the ultra fine patterning technologies in the manufacturing of semiconductor devices. We are now in the moment of transition from the stronghold of KrF to the prospective of ArF. In this paper, we applied ArF process to the real DRAM devices of 90nm node. We proved good pattern fidelity and device performance. The ArF process, however, has still some weak points - resist shrinkage and LER (Line Edge Roughness). Resist shrinkage is very crucial problem for measuring CD. To overcome it, we applied ASC (Anti-Shrinkage Coating) process to ArF resist and improved the CD measurement. LER also becomes an issue, as the design rule is shrink. It is found that they are very dependent on resist type. However, it could be cured effectively by VUV treatment. Finally we will mention the current status of low k1 factor and the future lithographic strategy of which technologies will be most feasible based on current situation.

Validation of ArF Chromeless PSM in the Sub-100 nm Node DRAM Cell

Process windows, MEEF (Mask Error Enhancement Factor), flare, aberration effect of the CLM (Cr-less PSM) were measured by the simulations and experiments for the various DRAM cell patterns compared with 6% transmittance HTPSM in the ArF lithography. We designed CLM layouts of sub 100nm node DRAM cells concerning the mask manufacturability, maximizing the NILS (Normalized Image Log Slope) and minimizing the MEEF with a semi-automatic OPC tool. Isolation, line and space and various contact patterns showed increasing process windows compared with HTPSM and this strongly depended on the layout design. Using 0.75 NA ArF Scanner, CLM showed NILS reduction by about 10% in the presence of lens aberration and flare, which reduced DoF margin by about 0.1~0.2 μm depending on the layer. So the critical layers in sub 100 nm node DRAM satisified 10% of EL (Exposure Latitude) and 0.4 μm of DoF (Depth of Focus) margin.

One step forward to maturity of AF (assistant feature)-OPC in 100-nm level DRAM application

For 100nm-level patterning using optical lithography, high NA system and various RETs such as PSM, off-axis illumination and OPC are obviously required. In particular, assistant feature (AF)-OPC is indispensable to overcome narrow depth of focus (DOF) caused by iso-dense bias and to compensate for linearity difference under the given OAI condition. Previously we reported the application of AF-OPC in DRAM process with 120nm design rule. The extraction of OPC rule and the feasibility of AF-OPC were successfully confirmed by experimental method in real process. In this paper, more comprehensive and aggressive AF-OPC rule is investigated. The old rule is modified in order to obtain larger common DOF. TO avoid dead zone that means discontinuity between dense line and semi-dense line, we apply a comprehensive rule such as insertion of AF between the neighboring main patterns as many as possible. As a result, the discontinuity of OPC application, which is used with or without AF in the boundary region, is effectively minimized. Also, polygon-shaped AF is used to improve DOF of special main pattern. And then, the mask specification and the behavior of isolated line pattern are predicted in case of very high NA KrF and ArF lithography by simulation result. Considering 100nm design rule, the decrease of common DOF is expected to be severer than now. Finally, the optimum AF-OPC rules such as AF size, space and shape are available and shown in case of very high NA KrF and ArF lithography.