Jungjin Park

Integrate-and-Fire Neuron Circuit and Synaptic Device with Floating Body MOSFETs

We propose an integrate-and-fire neuron circuit and synaptic device with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET for biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has short-term and long-term memory in a single silicon device [1]. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period using floating body MOSFET [2]. The neuron circuit and the synaptic device are connected using current mirror circuit for summation of post synaptic pulses.

Silicon-Based Floating-Body Synaptic Transistor With Frequency-Dependent Short- and Long-Term Memories

A new synaptic transistor was fabricated with two separated gates based on a FinFET structure in order to mimic short- and long-term memories in a biological synapse and connect with a postsynaptic neuron circuit directly. The transition between short- and long-term memories occurred after applying repetitive input pulses and strongly depended upon intervals between input pulses. These findings indicate that it has very similar learning characteristics with a biological synapse and the possibility as a synaptic device in neuromorphic systems.

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

Simulation Study on Silicon-Based Floating Body Synaptic Transistor with Short- and Long-Term Memory Functions and Its Spike Timing-Dependent Plasticity

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

Multi-threshold voltages in ultra thin-body devices by asymmetric dual-gate structure

Control of threshold voltage (V T) by asymmetric dual-gate structure is investigated. Two separated gates are successfully fabricated through two-step chemical mechanical polishing (CMP) processes. Silicon fin width is determined as same as the thickness of oxide sidewall spacer. V T of the device is modulated by how many charges are trapped in the nitride layer of the second gate stack (G2) through applying programming pulses to G2. They affect the formation of electron channel on the first gate (G1) side. Additionally, the efficiency of this technique is analyzed by simple capacitance network. The thinner body is the more effective the proposed V T control method is. It is noteworthy that this method can be used without ultra thin buried oxide (BOX) structure and additional biasing scheme.

Compact Neuromorphic System With Four-Terminal Si-Based Synaptic Devices for Spiking Neural Networks

In this paper, we propose a compact neuromorphic system that can work with four-terminal Si-based synaptic devices for spiking neural networks. The system consists of Si-based floating-body synaptic transistors and integrate-and-fire neuron circuit. The synaptic device can change its weight using floating-body effect and charge injection into the floating gate. The neuron circuit integrates signals from the synaptic devices through current mirrors and generates an action-potential when the integrated signal value exceeds a threshold value. The generated action potential that is transmitted to postsynaptic neurons is simultaneously returned to the back gate of the synaptic device for the change of weight based on spike-timing-dependent-plasticity. As the four-terminal synaptic device can transmit preneuron signals and change its weight at the same time, we can constitute the compact neuromorphic system without additional switches or logic operation and emulate the operation of neuron with a minimum number of devices and power dissipation (~3 pJ).

Neuron Circuit Using a Thyristor and Inter-neuron Connection with Synaptic Devices

We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synapticneuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.

Integrate-and-Fire Neuron Circuit and Synaptic Device using Floating Body MOSFET with Spike Timing-Dependent Plasticity

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrateand- Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

Integrate-and-fire neuron circuit and synaptic device with a floating body MOSFET

We propose an integrate-and-fire neuron circuit and synaptic device with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET for biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has short-term and long-term memory in a single silicon device [1]. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period using floating body MOSFET [2]. The neuron circuit and the synaptic device are connected using current mirror circuit for summation of post synaptic pulses.

Extraction of Location and Energy Level of the Trap Causing Random Telegraph Noise at Reverse-Biased Region in GaN-Based Light-Emitting Diodes

In order to analyze the trap in the multi-quantum well (MQW) consisting of a GaN-InGaN pair, the extraction of the location and energy level of the trap using random-telegraph-noise experiment was presented. Through the simplification of the band diagram of the complex MQW into an approximate structure, the equation for the location and the energy level of the trap was expressed as simply as possible. As a result of the extraction, we found that the traps of each sample are located very close to p-GaN or n-GaN interfaces.