Sungmin Hwang

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

Analog Synaptic Behavior of a Silicon Nitride Memristor

In this paper, we present a synapse function using analog resistive-switching behaviors in a SiNx-based memristor with a complementary metal-oxide-semiconductor compatibility and expandability to three-dimensional crossbar array architecture. A progressive conductance change is attainable as a result of the gradual growth and dissolution of the conducting path, and the series resistance of the AlOy layer in the Ni/SiNx/AlOy/TiN memristor device enhances analog switching performance by reducing current overshoot. A continuous and smooth gradual reset switching transition can be observed with a compliance current limit (>100 μA), and is highly suitable for demonstrating synaptic characteristics. Long-term potentiation and long-term depression are obtained by means of identical pulse responses. Moreover, symmetric and linear synaptic behaviors are significantly improved by optimizing pulse response conditions, which is verified by a neural network simulation. Finally, we display the spike-timing-dependent plasticity with the multipulse scheme. This work provides a possible way to mimic biological synapse function for energy-efficient neuromorphic systems by using a conventional passive SiNx layer as an active dielectric.

Simulation Study on Silicon-Based Floating Body Synaptic Transistor with Short- and Long-Term Memory Functions and Its Spike Timing-Dependent Plasticity

In this work, a novel silicon (Si) based floating body synaptic transistor (SFST) is studied to mimic the transition from short-term memory to long-term one in the biological system. The structure of the proposed SFST is based on an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) with floating body and charge storage layer which provide the functions of short- and long-term memories, respectively. It has very similar characteristics with those of the biological memory system in the sense that the transition between short- and long-term memories is performed by the repetitive learning. Spike timing-dependent plasticity (STDP) characteristics are closely investigated for the SFST device. It has been found from the simulation results that the connectivity between pre- and post-synaptic neurons has strong dependence on the relative spike timing among electrical signals. In addition, the neuromorphic system having direct connection between the SFST devices and neuron circuits are designed.

Multi-threshold voltages in ultra thin-body devices by asymmetric dual-gate structure

Control of threshold voltage (V T) by asymmetric dual-gate structure is investigated. Two separated gates are successfully fabricated through two-step chemical mechanical polishing (CMP) processes. Silicon fin width is determined as same as the thickness of oxide sidewall spacer. V T of the device is modulated by how many charges are trapped in the nitride layer of the second gate stack (G2) through applying programming pulses to G2. They affect the formation of electron channel on the first gate (G1) side. Additionally, the efficiency of this technique is analyzed by simple capacitance network. The thinner body is the more effective the proposed V T control method is. It is noteworthy that this method can be used without ultra thin buried oxide (BOX) structure and additional biasing scheme.

Spectroscopic ellipsometry study on E2 peak splitting of Si–Ge short period superlattices

We report spectroscopic ellipsometry (SE) studies on (Si)2(Ge)12, (Si)6(Ge)2, and (Si)12(Ge)2 short period superlattices (SLs) whose optical response has not been reported yet. Multilayer calculations enabled us to determine the dielectric response of the superlattice layers. We report the clear observation of splitting of the E2 peak in (Si)m(Ge)n superlattices contrary to the previous SE report that the separation was observed only in larger period SLs.

InGaN/GaN light-emitting diode having direct hole injection plugs and its high-current operation

The light-emitting diode (LED) with an improved hole injection and straightforward process integration is proposed. p-type GaN direct hole injection plugs (DHIPs) are formed on locally etched multiple-quantum wells (MQWs) by epitaxial lateral overgrowth (ELO) method. We confirm that the optical output power is increased up to 23.2% at an operating current density of 100 A/cm2. Furthermore, in order to identify the origin of improvement in optical performance, the transient light decay time and light intensity distribution characteristics were analyzed on the DHIP LED devices. Through the calculation of the electroluminescence (EL) decay time, internal quantum efficiency (IQE) is extracted along with the recombination parameters, which reveals that the DHIPs have a significant effect on enhancement of radiative recombination and reduction of efficiency droop. Furthermore, the mapping PL reveals that the DHIP LED also has a potential to improve the light extraction efficiency by hexagonal pyramid shaped DHIPs.

Compact Neuromorphic System With Four-Terminal Si-Based Synaptic Devices for Spiking Neural Networks

In this paper, we propose a compact neuromorphic system that can work with four-terminal Si-based synaptic devices for spiking neural networks. The system consists of Si-based floating-body synaptic transistors and integrate-and-fire neuron circuit. The synaptic device can change its weight using floating-body effect and charge injection into the floating gate. The neuron circuit integrates signals from the synaptic devices through current mirrors and generates an action-potential when the integrated signal value exceeds a threshold value. The generated action potential that is transmitted to postsynaptic neurons is simultaneously returned to the back gate of the synaptic device for the change of weight based on spike-timing-dependent-plasticity. As the four-terminal synaptic device can transmit preneuron signals and change its weight at the same time, we can constitute the compact neuromorphic system without additional switches or logic operation and emulate the operation of neuron with a minimum number of devices and power dissipation (~3 pJ).

Spiking Neural Networks with Unsupervised Learning Based on STDP Using Resistive Synaptic Devices and Analog CMOS Neuron Circuit

We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD). The resistive synaptic device had gradual set and reset characteristics and the conductance was adjusted by spike-timing-dependent-plasticity (STDP) learning rule. We carried out circuit simulation of synaptic device and CMOS neuron circuit. And we have developed an unsupervised spiking neural networks (SNNs) for 5 × 5 pattern recognition and classification using the neuron circuit and synaptic devices. The hardware-based SNNs can autonomously and efficiently control the weight updates of the synapses between neurons, without the aid of software calculations.

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy c...

Back biasing effects in a feedback steep switching device with charge spacer

In this work, the back gate bias (V_BG) effect on the threshold voltage (V_T) of a feedback steep switching device has been studied using TCAD simulations. Unlike other devices, there was a region where V_T of a feedback switching device was increased even though V_BG was increased due to the raised hole barrier. These findings indicate that a new V_T modulation method is required other than ground plane or V_BG schemes.