Junichi Tsuchimoto

Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET

F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET. Mobility degradation is not accompanied and drive current is increased by 180%. From analytical and electrical characterization, the Vth shift is attributed to change in trap density

Local Temperature Rise during Laser Induced Etching of Gallium Arsenide in SiCl4 Atmosphere

Localized etching of GaAs using an argon laser beam in an SiCl4 atmosphere has been performed for various laser powers to investigate the threshold power, i.e., the minimum local temperature, for pyrolytic etching. Local temperature rise during laser induced etching was measured by the peak shift of in situ photoluminescence and was also estimated by solving the three dimensional heat equation. It was found that the threshold power for pyrolytic etching at an SiCl4 pressure of 76 Torr was about 0.25 W, turning out to be about 190°C, which was in good agreement with the calculated temperature.

Suppression of Anomalous Gate Edge Leakage Current by Control of Ni Silicidation Region using Si Ion Implantation Technique

It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby current and yield for 65nm-node SRAM are greatly improved. This novel technique has high potential for 45nm and 32nm CMOS technology

Maskless Dry Etching of Gallium Arsenide with a Submicron Line-Width by Laser Pyrolysis in CCl4 Gas Atmosphere

Localized etching of GaAs using Ar ion laser beams focused down to 1.2 µm has been performed in a CCl4 atmosphere to realize a maskless dry etching process with a submicron line-width. It was found that etched line patterns with a line-width down to 0.6 µm could be obtained by laser irradiation with a power of 80 mW in a CCl4 atmosphere at a pressure or 30 Torr. Etching rates ranged from 2.2 to 6.3 µm/s, which were greater by up to 4 orders of magnitude than those of ultraviolet laser photolysis.

Low-resistive and homogenous NiPt-silicide formation using ultra-low temperature annealing with microwave system for 22nm-node CMOS and beyond

A novel NiPt-silicide formation using microwave annealing (MWA) is proposed, and superior properties of NiPt silicide in ultra-shallow junction (USJ) are demonstrated for the first time. MWA is suitable for the thin NiPtSi formation with its stable and ultra-low temperature (less than 250 °C) heating. The anomalous Ni diffusion during the NiPtSi formation is considered to be suppressed because MW system heats Si substrates selectively. As a result, low-resistive and homogeneous NiPtSi can be formed, and the increase of the junction leakage current due to the abnormal NiPt-silicide growth is successfully suppressed in USJ. This superior technique is quite promising for achieving 22nm-node CMOS and beyond.

80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Double offset-implanted source/drain extension and 550/spl deg/C silicon nitride deposition for sidewall and borderless contact have been applied to sub-0.1 /spl mu/m CMOS for improvement of short channel effect as well as parasitic resistance. Consequently, 830/400 /spl mu/A//spl mu/m drive current with 2.5 nm gate insulator has been achieved under 1 nA//spl mu/m off-leakage at 1.5 V operation with short channel tolerance to 80 nm gate length.

Impact of additional Pt and NiSi crystal orientation on channel stress induced by Ni silicide film in metal?oxide?semiconductor field-effect transistors

The impact of additional Pt and Ni monosilicide (NiSi) crystal orientation on channel stress from Ni silicide in metal–oxide–semiconductor field-effect transistors (MOSFETs) has been demonstrated. The channel stress generation mechanism can be explained by the NiSi crystal orientation. In pure Ni silicide films, the channel stress in the p-type substrate is much larger than that in the n-type one, since the NiSi a-axis parallel to the channel direction is strongly aligned on the p-type substrate compared with on the n-type one. On the other hand, in NiPt silicide films, the difference in the channel stress between the p- and n-type substrates is small, because the NiSi crystal orientation on the p-type substrate is similar to that on the n-type one. These results can be explained by the Pt segregation at the interface between the NiSi film and the Si surface. Segregated Pt atoms cause the NiSi b-axis to align normal to the Si(001) surface in the nucleation step owing to the expansion of the NiSi lattice spacing at the NiSi/Si interface. Furthermore, the Pt segregation mechanism is considered to be caused by the grain boundary diffusion in the Ni2Si film during NiSi formation. We confirmed that the grains of Ni2Si on the p-type substrate are smaller than those on the n-type one. The Ni2Si film on the p-type substrate has more grain boundary diffusion paths than that on the n-type one. Therefore, the amount of Pt segregation at the NiSi/Si interface on the p-type substrate is larger than that on the n-type one. Consequently, the number of NiSi grains with the b-axis aligned normal to the Si(001) in the p-type substrate is larger than that in the n-type one. As a result, the channel stress induced by NiPt silicide in PMOS is larger than that in NMOS. According to this mechanism, controlling the Pt concentration at the NiSi/Si interface is one of the key factors for channel stress engineering.

Analysis of Channel Stress Induced by NiPt-Silicide in Metal–Oxide–Semiconductor Field-Effect Transistor and Its Generation Mechanism

Channel stress induced by NiPt-silicide films in metal–oxide–semiconductor field-effect transistors (MOSFETs) was demonstrated using UV-Raman spectroscopy, and its generation mechanism was revealed. It was possible to accurately measure the channel stress with the Raman test structure. The channel stress depends on the source/drain doping type and the second silicide annealing method. In order to discuss the channel stress generation mechanism, NiPt-silicide microstructure analyses were performed using X-ray diffraction analysis and scanning transmission electron microscopy. The channel stress generation mechanism can be elucidated by the following two factors: the change in the NiSi lattice spacing, which depends on the annealing temperature, and the NiSi crystal orientation. The analyses of these factors are important for controlling channel stress in stress engineering for high-performance transistors.

Anomalous Gate-Edge Leakage Current in nMOSFETs Caused by Encroached Growth of Nickel Silicide and Its Suppression by Confinement of Silicidation Region Using Advanced

The anomalous gate-edge leakage current in n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs), which is caused by the encroached growth of nickel silicide across the p-n junction, is first reported. Furthermore, this encroached growth, which is caused by the isotropic and rapid diffusion of Ni atoms during the silicidation annealing, is successfully suppressed by the advanced Si+ ion-implantation (Si-I.I.) technique. Using the Si-I.I. technique, both the anisotropic silicidation to the perpendicular direction and the phase transition from Ni2Si to NiSi are enhanced by the introduction of damaged layers into Si substrates, such as vacancy and amorphous Si layers, and as a result, the silicidation region is confined at the source and drain regions. In addition, we propose a new evaluation method for the quantitative analysis of the encroached growth based on its growth properties, namely, the variability of encroached growths, which is three standard deviations of the roughness at silicide edges. The usefulness of this simple analysis for a large number of nMOSFETs is also demonstrated.

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We have investigated a polycrystalline silicon (poly-Si)/chemical vapor deposited titanium nitride (CVD-TiN) stacked structure as a metal gate with a high-k for p-type metal insulator semiconductor field effect transistors (p-MISFETs). A divided-CVD method provided an appropriate effective work function (4.9–5.2 eV) on HfSiON for p-MISFETs. However, the deposition of poly-Si on CVD-TiN films shifted the effective work function to a midgap (~4.6 eV), and Ti, Hf, and Si diffused into poly-Si/CVD-TiN/high-k structures during poly-Si deposition. Then, we found that an increase in the deposition temperature of CVD-TiN films and the insertion of a physical vapor deposited (PVD)-TiN film between the poly-Si and CVD-TiN layers are effective in suppressing these diffusions. In particular, the insertion of the PVD-TiN film provided an appropriate effective work function of 4.9 eV. Therefore, we found that the diffusion control techniques for poly-Si/TiN/high-k stacked structures are highly effective for obtaining the appropriate work function for p-MISFETs.