Junjiang Lei

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Directed self-assembly compliant flow with immersion lithography: from material to design and patterning

Abstract. We present a directed self-assembly (DSA) compliant flow for contact/via layers with immersion lithography assuming the graphoepitaxy process for the cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use template error enhancement factor to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data show that it is promising to achieve two-mask solution with DSA for the contact/via layer using 193i at 5 nm node.

Model-based OPC using the MEEF matrix II

In the traditional OPC (Optical Proximity Correction) procedure, edges in a layout are broken into fragments and each fragment is iteratively adjusted by multiplying its EPE (Edge Placement Error) with a carefully selected or calculated feedback. However, the ever-shrinking technology nodes in recent years bring stronger fragment to fragment interaction. The feedback tuning approach driven by a single fragment EPE is no longer sufficient to achieve good pattern fidelity with reasonable turn-around-time. Various novel techniques such as matrix OPC [1, 2] have been developed in the past to incorporate the influence of neighboring fragments into each fragment’s movement. Here we introduce a neighboraware feedback controller for full chip level OPC applications, following the concept and algorithms of the matrix OPC that were laid out in Cobb and Granik’s work [1]. We present experimental results and discuss the benefits and challenges of the proposed feedback controller.

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.

Design technology co-optimization for N14 Metal1 layer

Design and technology co-optimization (DTCO) is a new technology method, which takes the manufacturing process limitations, mainly lithography, into account during the early design stage. This paper demonstrates a DTCO workflow which includes layout generation, pattern analysis, hotspot library establishment and design rule optimization mainly. And the paper also gives an example about the method to optimize the design rule related to SADP decomposition. The DTCO workflow can generate friendly layout and find the hotspot patterns in order to avoid the unfriendly design in the advance work and make sure that the layout can be manufactured by the current process level. The DTCO workflow proposed in this paper is an efficient solution for refining the design rules for 14/10 nm tech node Metal1 layer.

Directed Self Assembly (DSA) compliant flow with immersion lithography: from material to design and patterning

In this paper, we present a DSA compliant flow for contact/via layers with immersion lithography assuming the grapho-epitaxy process for cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use Template Error Enhancement Factor (TEEF) to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data shows that it is promising to achieve 2-mask solution with DSA for the contact/via layer using 193i at 5nm node.

Hotspots fixing flow in NTD process by using DTCO methodology at 10nm metal 1 layer

This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.

Design technology co-optimization for 14/10nm metal1 double patterning layer

Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.

Dynamic feedback controller for optical proximity correction

A dynamic feedback controller for Optical Proximity Correction (OPC) in a random logic layout using ArF immersion Lithography is presented. The OPC convergence, characterized by edge placement error (EPE), is subjected to optimization using optical and resist effects described by calibrated models (Calibre® nmOPC simulation platform). By memorizing the EPE and Displacement of each fragment from the preceding OPC iteration, a dynamic feedback controller scheme is implemented to achieve OPC convergence in fewer iterations. The OPC feedback factor is calculated for each individual fragment taking care of the cross-MEEF (mask error enhancement factor) effects. Due to the very limited additional computational effort and memory consumption, the dynamic feedback controller reduces the overall run time of the OPC compared to a conventional constant feedback factor scheme. In this paper, the dynamic feedback factor algorithm and its implementation, as well as testing results for a random logic layout, are compared and discussed with respect to OPC convergence and performance.