George P. Lippincott

Directed self-assembly graphoepitaxy template generation with immersion lithography

Abstract. We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.

Model-based OPC using the MEEF matrix II

In the traditional OPC (Optical Proximity Correction) procedure, edges in a layout are broken into fragments and each fragment is iteratively adjusted by multiplying its EPE (Edge Placement Error) with a carefully selected or calculated feedback. However, the ever-shrinking technology nodes in recent years bring stronger fragment to fragment interaction. The feedback tuning approach driven by a single fragment EPE is no longer sufficient to achieve good pattern fidelity with reasonable turn-around-time. Various novel techniques such as matrix OPC [1, 2] have been developed in the past to incorporate the influence of neighboring fragments into each fragment’s movement. Here we introduce a neighboraware feedback controller for full chip level OPC applications, following the concept and algorithms of the matrix OPC that were laid out in Cobb and Granik’s work [1]. We present experimental results and discuss the benefits and challenges of the proposed feedback controller.

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.

Cross-MEEF assisted SRAF print avoidance approach

Sub-resolution assist features (SRAFs) have become an integral part of low-k lithography’s resolution enhancement techniques (RET). Gradually maturing EUV technology indicates that SRAF insertion might be necessary for 5nm technology nodes and below. In mask synthesis flows, during the correction step, an SRAF print avoidance (SPA) algorithm is relying on detection of printing predicted by model based simulation. In this paper we are presenting a cross-MEEF based SPA approach that offers elimination of SRAF printing while minimizing impact on process window.

A novel full chip process window OPC based on matrix retargeting

Process window OPC (PWOPC) is widely used in advanced technology nodes as one of the most important resolution enhancement techniques (RET).1 PWOPC needs to consider not only edge placement error (EPE) from nominal condition simulations, but also constraints based on process variation simulations, such as pinch and bridge related requirements based on process variation band (PVBAND). Those constraints can be challenging to meet as feature size continues to shrink in advanced nodes. In this paper a novel matrix retargeting based PWOPC was developed to find optimal OPC solutions by solving constraints-based matrix and applying minimal retargeting as needed.2 Experiment results showed enhanced process window and reasonable performance.

Flexible MRC rules for OPC

Optical Proximity Correction (OPC) can be formulated as a constrained optimization problem. The constraints are mask constraint rules for space and width. These are sometimes called Mask Rule Checks (MRC), or Design Rule Checks (DRC). At 90nm and below, intelligent constraint handling is required for good OPC. In this paper, we show a technique for OPC constraint checking which is built in to the OPC feedback algorithm. The system is flexible enough to allow relaxed rules for corner-to-corner checking versus edge-to-edge checking. Also, the system can categorize checks by the length of the edges being compared. Lastly, the system can create special checks from line-ends to other features, or any user-defined edge type to any other user-defined edge type. In addition, we present a method for multiple layer enclosure rules which can be used for multiple exposure OPC. These enclosure constraints are useful for assurance of overlay tolerance.