K. Akarvardar

Design Considerations for Complementary Nanoelectromechanical Logic Gates

The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at VDD = 1.5 V while occupying an area as small as 0.03 mum2.

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed.

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1ki2) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.

Investigation of the four-gate action in G/sup 4/-FETs

The four-gate silicon-on-insulator transistor (G/sup 4/-FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G/sup 4/-FET are analyzed, based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications.

Efficient FPGAs using nanoelectromechanical relays

Nanoelectromechanical (NEM) relays are promising candidates for programmable routing in Field-Programmable-Gate Arrays (FPGAs). This is due to their zero leakage and potentially low on-resistance. Moreover, NEM relays can be fabricated using a low-temperature process and, hence, may be monolithically integrated on top of CMOS circuits. Hysteresis characteristics of NEM relays can be utilized for designing programmable routing switches in FPGAs without requiring corresponding routing SRAM cells. Our simulation results demonstrate that the use of NEM relays for programmable routing in FPGAs can simultaneously provide 43.6% footprint area reduction, 37% leakage power reduction, and up to 28% critical path delay reduction compared to traditional SRAM-based CMOS FPGAs at the 22nm technology node.

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G4-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poissons equation. The model is used to obtain the surface threshold voltage of the G4-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices

Ultralow Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches

A novel nonvolatile nanoelectromechanical (NEM) memory (nRAM) is introduced. Differently than the previously proposed NEM memories, the nRAM achieves the nonvolatility via workfunction engineering and eliminates the need for cell selection devices in a crossbar array using a displacement current-based read scheme. Furthermore, the configuration of the nRAM is such that the elastic potential energy due to the beam bending is reversibly used for switching, which enables to combine ultralow operation voltages with high switching speed. For F = 20 nm feature size and optimized margins, the nRAM cell is estimated to operate at plusmn180 mV, dissipate 10 aJ switching energy, and achieve < 10 ns switching delay.

Depletion-All-Around Operation of the SOI Four-Gate Transistor

In the silicon-on-insulator four-gate transistors (G4-FETs), the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxide-semiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The G4-FET properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling

High-temperature performance of state-of-the-art triple-gate transistors

High-temperature performance of state-of-the-art n-channel triple-gate transistors with 15 nm fin-width, 60 nm fin-height, undoped body, high-k gate dielectric and metal gate is reported. The degradation of the on-current, transconductance and subthreshold swing, the shift in threshold voltage, the increase in gate/drain leakages and off-current with the temperature are analyzed up to 200 °C. The comparison of short- and long-channel devices and the overall excellent performance at high temperature are outlined.

Evidence for reduction of noise and radiation effects in G/sup 4/-FET depletion-all-around operation

The low noise and radiation-hard operation of the SOI four-gate transistor (G/sup 4/-FET) is experimentally demonstrated. When operated in depletion-all-around (DAA) mode, the G/sup 4/-FET drain current flows in the middle of the silicon film, far from the interfaces. The influence of oxide and interface traps on the conduction channel is suppressed by biasing the front and back gates in depletion or, even better, in inversion. Systematic data show a significant reduction of low-frequency noise as well as a quasi-insensitivity to total-dose radiation effects, up to 10 Mrad. These features come along with superior static characteristics in DAA mode and are attractive for G/sup 4/-FET-based analog circuits.