K.-F. Becker

Stackable system-on-packages with integrated components

In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in the Z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.

Large area embedding for heterogeneous system integration

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing with potential for low cost applications. Wafer level embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of compression and transfer molding techniques for multi chip embedding in combination with large area and low cost redistribution technology from printed circuit board manufacturing as adapted for Chip-in-Polymer applications. The work presented is part of the German governmental funded project SmartSense. Embedding by transfer molding is a well known process for component embedding that is widely used for high reliable microelectronics encapsulation. However, due to material flow restrictions transfer molding does not allow large area encapsulation, but offers a cost effective technology for embedding on a medium size scale as known e.g. from MAP (molded array packaging) molding (typically with sizes up to 60 × 60 mm2). In contrast, compression molding is a relatively new technology that has been especially developed for large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically up to 8” or even up to 12”. Wiring of these embedded components is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - no matter which shape the embedded components areas are: a compression molded wafer, larger rectangular areas or smaller transfer molded systems (MAP). Typical process flow for RCC redistribution is lamination of RCC, via drilling to die pads by laser, galvanic Cu via filling, conductor line and pad formation by Cu etching, soldermask and solderable surface finish application - all of them standard PCB processes. The feasibility of the technology is demonstrated by the fabrication of a Land Grid Array (LGA) type package with two embedded dies. First step is a high precision die placement on an intermediate carrier. For embedding, both compression molding and transfer molding are used and directly compared with regards to material properties, processing, resulting die shift and warpage after molding. Reliability testing including MSL testing, temperature cycling, and humidity storage has been performed with LGA packages manufactured using the different technologies. The reliability potential and failure modes are intensively discussed and backed by destructive and non destructive failure analysis. Finally, an outlook for the integration of through mold vias into RCC redistribution process flow is given showing also the potential for package stacking.

From wafer level to panel level mold embedding

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. Mold embedding is currently done on wafer level, typically with diameters of 8“ to 12”, for future process optimization, PCB technologies offer the potential of real large areas up to 610 × 457 mm2. For mold embedding as e.g. for fan-out wafer level packaging compression molding equipment is used in combination with liquid, granular or sheet epoxy molding compounds, with the boundary condition, that mold processes do need a product specific tool (with defined diameter & thickness). Within this paper the potential of tool-less lamination processes, a standard in PCB manufacturing, is evaluated. Lamination is done in panel format using well-known molding compounds from wafer level compression molding. To evaluate the potential of todays encapsulants for large area embedding processes, different liquid, granular and sheet molding compounds have been intensively evaluated on their processability, on process & material induced die shift and on resulting warpage - all on panel level. Acting as an interconnection layer, PCB based redistribution technologies using lamination of resin coated copper (RCC) films are used. Within the paper, different RCC materials are introduced and discussed concerning their reliability potential based on the available layer thicknesses and thermo-mechanical material properties. The feasibility of the proposed technologies is demonstrated using a two chip package. Dies are embedded in panel size by lamination technologies. Subsequently the wiring is done by lamination of an RCC film over the embedded components and on the panel backside for double sided redistribution. In a process flow also similar to conventional PCB manufacturing μvias to the die pads and through mold vias are drilled using a UV laser and are metalized by Cu-electroplating in one step. This way dies are connected to the front copper layer as well as front to backside of the panel. Conductor lines and pads are formed by Cu etching. Finally, a solder mask and a solderable surface finish are applied. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. In summary this paper describes the potential to move from wafer level to panel level mold embedding technology in combination with PCB based redistribution processes. The technology described offers a cost effective packaging solution for e.g. single chip packages as well as for future sensor/ASIC systems or processor/memory stacks in volume production.

Improved Reliability of Leadfree Flip Chip Assemblies Using Direct Underfilling by Transfer Molding

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Transfer molding is the standard process for a highly reliable encapsulation of leaded and area array packages as BGAs or CSPs. Advanced materials and process developments now allow the use of transfer molding technology for direct underfilling and / or overmolding of Flip Chip assemblies. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing or jetting is required. Molded Flip Chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. Trends of the market drive towards SIPs with an integration of different devices. Therefore the highly reliable encapsulation of these hybrid packages with inhomogeneous topography is the goal. For testing the reliability limits and the determination of failure mechanism of molded Flip Chips a test vehicle has been designed at Fraunhofer IZM.

High temperature potential of flip chip assemblies for automotive applications

Flip chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products as cellular phones or GPS devices. The upper temperature limits for such applications range from 80 /spl deg/C to a maximum of 125 /spl deg/C. To widen the application range of flip chip technology and to address the volume market of automotive and industrial electronics, the development of high temperature capable assemblies is crucial. Typical scenario for the integration of electronics into a car is a control unit in the engine compartment, where ambient temperatures are around 150 /spl deg/C, package junction temperatures may range from 175 /spl deg/C to 200 /spl deg/C and peak temperature may exceed these values. When using flip chip technology under high temperature conditions, major challenges are found in the application of interconnect media and supporting polymers. At elevated temperatures, the intermetallic phase formation of lead-free solders might lead to a reliability decrease, where polymeric materials as substrate and encapsulant do potentially show mismatched thermo-mechanical properties or material degradation and thus reliability is reduced. Literature does typically describe flip chip technologies behavior on organic substrates for consumer applications, but almost no information is available on the performance at temperatures beyond 125 /spl deg/C. Within the European project HOTCAR, dealing with high temperature electronics for automotive use in general, a German consortium consisting of an IC manufacturer (IFX), two technology users (Siemens VDO & Temic) and a research institute (Fraunhofer IZM) have cooperated to evaluate the high temperature potential of lead-free flip chip technology for automotive applications. According to automotive demands, an experimental study on the suitability of advanced Underfill encapsulants for high temperature has been performed. With the outcome of this pre-study, two promising underfill materials were selected and used in a test run with an automotive test vehicle. This comprises an automotive grade /spl mu/Controller mounted on a substrate manufactured according to automotive standards, as the major system components. Solder material used was SnAg with a Ni UBM in combination with two different substrate finishes NiAu and immersion Sn. These test devices were submitted to temperature cycles according to automotive specifications with a maximum temperature of 150 /spl deg/C. Intermetallic phase formation was studied after high temperature storage by cross sections and shear tests. Typical failure modes for flip chip failure have been identified and are described in detail. The experimental reliability investigations were backed by thermo-mechanical simulations. Taking advantage of the so-called submodelling technique, the solder joint behavior could be studied in detail for lead-free solders. Starting stress-free at 150 /spl deg/C, the calculations followed the real thermal cycling regime. As primary results, the accumulated equivalent creep strain and creep strain energy distributions were obtained. Based on Manson-Coffin-coefficients from recent experiments at IZM, mean cycles to failure (MCF) have been estimated for solder joint fatigue and compared with observed failure. In summary, a status of the high temperature potential of lead-free flip chip technology under automotive conditions is given and a first design guideline for high temperature automotive flip chip applications is provided.

Flip Chip molding - Recent progress in flip chip encapsulation

As the development of microelectronics is still driving towards further miniaturization, Flip Chip technology has been widely accepted as a means for. maximum miniaturization with additional advantages. These are shortest interconnect length for minimum signal disturbance and simultaneous interconnection leading to reduced process times especially for high I/O counts and for RF applications. Flip Chip technology allows for reliabilities required for automotive applications, but to achieve this goal, a plastic encapsulant, the so called underfiller, has to be used. Conventionally a liquid epoxy resin is dispensed near the Flip Chip and is driven by capillary action under the chip. New material developments for transfer molding allow now underfilling and overmolding in one single transfer molding step. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing is required. Molded Flip Chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. State of the art in FC molding is the encapsulation of Single Chip Packages as BGA or CSP. Trends of the market driving at SIPs with an integration of different devices as e.g. SMD and FC. Therefore the high reliable encapsulation of these hybrid packages with inhomogeneous topography is the future goal. For the qualification of Flip Chip Molding a test vehicle has been designed at Fraunhofer IZM. This test vehicle for process evaluation allows the encapsulation and underfilling of a single flip chip. Process development is described with a focus on Flip Chip and SIP molding challenges. Here the encapsulation process demands are filling of extremely small gaps without air entrapments, undisturbed bond integrity while molding at temperatures near melting point of the solder and increased pressures and venting of the mold. Device reliability demands are reduced warpage and optimum adhesion of the molding compound to solder mask, solder and die, even in harsh environment. Different materials available on the market are evaluated regarding process behavior and principal applicability for Flip Chip encapsulation. Nondestructive and destructive analysis is used to determine the failures occurring as voids and delaminations in initial state and during reliability investigations. In summary a status of the Flip Chip Molding technology is given.

Through mold via technology for multi-sensor stacking

With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8” to 12” in diameter, while future developments will deal with panel sizes up to 470 × 370 mm². The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components — whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating — all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lamination and were metalized together with the vias for chip interconnection. Reliability of the manufactured through mold vias with different via diameters and pitches was evaluated by moisture sensitivity level [MSL] testing, temperature cycling and humidity storage and test vehicles were analyzed both non-destructively and destructively. Results show high reliability potential of the introduced through mold via technology as samples have passed MSL 1 and more than 3000 temperature cycles and 3000 hour humidity storage without any electrical failure. The embedding and stacking technology is demonstrated for a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by the through mold vias and soldered to a base substrate. Concluding, within this paper on mold embedded SiPs both is shown — the development of TMVs, an advanced and low cost 3D packaging feature and demonstration of use of this feature for the assembly of a functional 3D multi-sensor system, illustrating the miniaturization potential of 3D system integration.

Wafer level encapsulation - a transfer molding approach to system in package generation

Flip chip and wafer level CSP technology have been widely accepted as a means for maximum miniaturization. Both package types do not generally include an explicit encapsulation layer, but only die passivation and dielectric rewiring layers respectively. To fulfill the reliability demands of harsh environment applications, the use of an additional encapsulant is recommended. Processes for wafer level encapsulation include wafer level molding and wafer level liquid encapsulation, both bearing individual advantages and disadvantages. Within this paper both, high precision, high volume transfer molding and the rather low cost wafer level printing have been investigated, focusing on the feasibility of reliable wafer encapsulation and the suitability of current materials. This paper presents the process development and feasibility of transfer molding as wafer level encapsulation technology for single die packages as well as for SIP solutions.

Flip chip molding - highly reliable flip chip encapsulation

Flip chip technology has the shortest interconnect length for minimum signal disturbance and simultaneous interconnection leading to reduced process times especially for high I/O counts and for RF applications. Flip chip technology allows for reliabilities required for automotive applications, but to achieve this goal, a plastic encapsulant, the so called underfiller, has to be used. New material developments for transfer molding allow underfilling and overmolding in one single transfer molding step. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing is required. Molded flip chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. State of the art in FC molding is the encapsulation of single chip packages as BGA or CSP. Trends of the market drive towards SIPs with an integration of different devices as e.g. SMD and FC. Therefore the highly reliable encapsulation of these hybrid packages with inhomogeneous topography is the future goal. For the qualification of flip chip molding a test vehicle has been designed at Fraunhofer IZM. This test vehicle for process evaluation allows the encapsulation and underfilling of a single flip chip.

Reliability study of the Stud Bump Bonding flip chip technology on Molded Interconnect Devices

The Stud Bump Bonding (SBB) flip chip technology on Molded Interconnect Devices (MID) is a highly promising solution to the increasing demand for reliable interconnection technology at high temperatures, a miniaturized assembly and a reduction of costs and parts.