K. Hatasako

Wide Voltage Power Device implementation in O.25μm SOI BiC-DMOS

In this paper, a new SOI BiC-DMOS process based on the 0.25mum CMOS process is introduced. SOI and dielectric isolation enables implementation of wide voltage and various types of lateral power devices. For Nch devices, 40V/60V/ 80V/100V/170V LDMOS and 170V/200V lateral IGBT were developed. The drift layers of LDMOS are optimized respectively. The 0.25mum CMOS process helps not only to shrink low voltage class devices such as 40V LDMOS but also to improve the SOA characteristics of high voltage devices

Necessity of pulse hot carrier evaluation in suppressing self-heating effect for SOI smart power

Hot carrier (HC) reliability of SOI LDMOS suppressing self-heating effect was investigated. We evaluated an appropriate HC degradation by controlling junction temperature (Tj) within the temperature range the circuit is actually operated of. A gate pulse HC evaluation system was used to suppress the self-heating effect during HC stress. Pulse HC stress shows that the drain current shift is three times larger and the threshold voltage shift is 10 times smaller at Tj = 25°C than the shifts evaluated by means of DC stress. We find that pulse stress evaluation is essential when estimating degradations of actual circuit operating temperatures for SOI smart power. The degradation mechanism was also evaluated using a charge pumping measurement.

0.15µm BiC-DMOS technology with novel stepped-STI N-channel LDMOS

We developed a state-of-the-art BiC-DMOS process using 0.15µm technology. High-voltage MOSFETs were embedded in our standard 0.15µm CMOS process with a 0.13µm high density NVM. More intelligent mixed signal devices can flexibly be realized by this technology. Moreover, the reliability of n-ch LDMOS is markedly improved by the novel structure of stepped-STI LDMOS.

Practical approaches to improve thermal SOA for smart power IC

In this paper, approaches to improve thermal SOA (T-SOA) of LDMOS have been presented. We show three important points for T-SOA based on experimental data. Firstly, improvement of thermal stability, which is expressed by simple index “α”; a ratio of drain current at 200°C divided by that at 25°C. Secondly, suppression of parasitic NPN action that causes device destruction and the correlation between failure energy and off-state leak current is studied. Thirdly, reduction of the thermal impedance. We examined an effect of Cu plate on wafer surface and a thinning effect of wafer thickness, and found thinner wafers were quite effective for long pulse energy.

Enhanced active protection technique for substrate minority carrier injection in Smart Power IC

In this paper, protection techniques against parasitic action due to minority carrier injection into substrate for Smart Power ICs have been presented. We investigated the protection efficiency of active type protection for various layout arrangements that are applicable to realistic IC, and found that the protection efficiency was strongly dependent on the layout. We propose the active type protection structure at collector side, which is effective at avoiding interferences from other components in realistic IC. We also found that separate type protection, which is one variation of the collector side protection, is more effective. The area penalty and the dependence of protection efficiency on temperature were also discussed.

Reliability study of thermal cycling stress on smart power devices

In this paper, we describe a smart power device degradation behavior under thermal cycling stress. An innovative test structure was developed, which faithfully reflects a stress state caused by the smart power device during operation. From our experiment, the device degraded after millions of fast thermal cycling pulses. We discovered that via destruction was the cause of the device degradation. For the duration of thermal cycling stress, the via resistance increased gradually, and finally increased rapidly at the point of millions of cycles. A failure via was observed, which was broken into two parts. Therefore, the via disconnection was considered to be due to thermo-mechanical stress or electro-migration. Some experiments were conducted, and we demonstrated that the via destruction dominated to the thermo-mechanical stress introduced by the thermal cycling stress.

Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

The lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor is one of the key elements of high-power devices. It is difficult to evaluate the degradation of an LDMOS at the required temperature range, because the self-heating effect of an LDMOS is too large for conventional evaluation in DC. In this paper, we report on the hot carrier degradation of an LDMOS under high-power operation, by investigating the LDMOS deterioration in the case that both the device structure and junction temperature (Tj) are different. The Tj of an LDMOS is controlled by operating the gate voltage (Vg) in pulse mode. Controlling Tj by operating Vg in pulse mode, the Tj dependence of hot carrier degradation under high-power operation can be evaluated widely and quantitatively. The threshold voltage (Vth) shift is observed according to the bias temperature mode irrespective of the device structure. On the other hand, the shift of drain current is affected by the length of the accumulation region under the gate electrode, and a relatively small increase in drain current (Ids) shift is observed with decreasing Tj. These phenomena are clarified from the results of charge pumping measurement and simulation.

Investigation of Via Degradation Behavior under Thermal Cycling Stress on Power Device

This paper describes via degradation behavior under thermal cycling stress on power device. The via resistance increased gradually under thermal cycling stress, and finally disconnected after millions of cycles. Via failure time under thermal cycling stress is shorter than under DC thermal stress. The failed via broke into two parts, with the top half being partly driven into the top aluminum line, and bottom half being driven into the bottom aluminum line. These results demonstrate that the degradation mechanism can be attributed to the repetition of expansion and contraction in the via and aluminum lines due to the thermal cycling stress, so-called thermo-mechanical stress. We have proofed that the cycles to failure depends on the temperature rise in the thermal cycling stress.