Tetsuya Nitta

Wide Voltage Power Device implementation in O.25μm SOI BiC-DMOS

In this paper, a new SOI BiC-DMOS process based on the 0.25mum CMOS process is introduced. SOI and dielectric isolation enables implementation of wide voltage and various types of lateral power devices. For Nch devices, 40V/60V/ 80V/100V/170V LDMOS and 170V/200V lateral IGBT were developed. The drift layers of LDMOS are optimized respectively. The 0.25mum CMOS process helps not only to shrink low voltage class devices such as 40V LDMOS but also to improve the SOA characteristics of high voltage devices

Necessity of pulse hot carrier evaluation in suppressing self-heating effect for SOI smart power

Hot carrier (HC) reliability of SOI LDMOS suppressing self-heating effect was investigated. We evaluated an appropriate HC degradation by controlling junction temperature (Tj) within the temperature range the circuit is actually operated of. A gate pulse HC evaluation system was used to suppress the self-heating effect during HC stress. Pulse HC stress shows that the drain current shift is three times larger and the threshold voltage shift is 10 times smaller at Tj = 25°C than the shifts evaluated by means of DC stress. We find that pulse stress evaluation is essential when estimating degradations of actual circuit operating temperatures for SOI smart power. The degradation mechanism was also evaluated using a charge pumping measurement.

0.15µm BiC-DMOS technology with novel stepped-STI N-channel LDMOS

We developed a state-of-the-art BiC-DMOS process using 0.15µm technology. High-voltage MOSFETs were embedded in our standard 0.15µm CMOS process with a 0.13µm high density NVM. More intelligent mixed signal devices can flexibly be realized by this technology. Moreover, the reliability of n-ch LDMOS is markedly improved by the novel structure of stepped-STI LDMOS.

Evolution of 200V lateral-IGBT technology

In this paper, an ideal lateral insulated gate bipolar transistor (LIGBT) using 0.25μm Silicon-on-insulator (SOI) BiC-DMOS process has been presented. We achieved the significant improvement of the 200V n-type LIGBT (n-LIGBT) current capability by applying hole and electron injection control, optimizing the N+/P+ widths in emitter region, shrinking the emitter-collector pitch, thinning the thickness of the gate insulator, reducing parasitic resistance and optimizing the profile of P-base impurity. The proposed device achieved the current increase by more than double compared with the previous technology. In addition, we improved short circuit capability of n-LIGBT by optimizing the structure and impurity profile. With the proposed n-LIGBT and other optimized devices, we have been able to realize 57% shrinkage in the PDP scan driver IC size compared with the previous one.

Practical approaches to improve thermal SOA for smart power IC

In this paper, approaches to improve thermal SOA (T-SOA) of LDMOS have been presented. We show three important points for T-SOA based on experimental data. Firstly, improvement of thermal stability, which is expressed by simple index “α”; a ratio of drain current at 200°C divided by that at 25°C. Secondly, suppression of parasitic NPN action that causes device destruction and the correlation between failure energy and off-state leak current is studied. Thirdly, reduction of the thermal impedance. We examined an effect of Cu plate on wafer surface and a thinning effect of wafer thickness, and found thinner wafers were quite effective for long pulse energy.

Enhanced active protection technique for substrate minority carrier injection in Smart Power IC

In this paper, protection techniques against parasitic action due to minority carrier injection into substrate for Smart Power ICs have been presented. We investigated the protection efficiency of active type protection for various layout arrangements that are applicable to realistic IC, and found that the protection efficiency was strongly dependent on the layout. We propose the active type protection structure at collector side, which is effective at avoiding interferences from other components in realistic IC. We also found that separate type protection, which is one variation of the collector side protection, is more effective. The area penalty and the dependence of protection efficiency on temperature were also discussed.

Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

The lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor is one of the key elements of high-power devices. It is difficult to evaluate the degradation of an LDMOS at the required temperature range, because the self-heating effect of an LDMOS is too large for conventional evaluation in DC. In this paper, we report on the hot carrier degradation of an LDMOS under high-power operation, by investigating the LDMOS deterioration in the case that both the device structure and junction temperature (Tj) are different. The Tj of an LDMOS is controlled by operating the gate voltage (Vg) in pulse mode. Controlling Tj by operating Vg in pulse mode, the Tj dependence of hot carrier degradation under high-power operation can be evaluated widely and quantitatively. The threshold voltage (Vth) shift is observed according to the bias temperature mode irrespective of the device structure. On the other hand, the shift of drain current is affected by the length of the accumulation region under the gate electrode, and a relatively small increase in drain current (Ids) shift is observed with decreasing Tj. These phenomena are clarified from the results of charge pumping measurement and simulation.

A novel bi-directional high voltage PMOS with trench gate structure (Waveform Depletion MOS: WDMOS) for 65V HVICs

In this paper, we propose a new bi-directional high voltage PMOSFET that improves a back-gate bias effect due to WDMOS (Waveform Depletion MOS) structure. In WDMOS structure, plural trench gates are adjacent each other. Therefore, the silicon between trench gates is easily depleted and a back-gate bias effect can be suppressed. We present excellent characteristics of the bi-directional high voltage PMOSFET with WDMOS structure.