T. Kuroi

Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

In this paper, a novel shallow trench isolation (STI) process is proposed for 45 nm node technologies and beyond. The major features of this process are the use of a fluorine-doped (F-doped) SiO2 film for gap filling and high-temperature rapid thermal oxidation (HT-RTO) for gate oxidation. Voidless filling of a narrow trench can be realized by F-doped high-density plasma chemical vapor deposition (F-doped HDP-CVD). Moreover, electron mobility degradation caused by STI stress and junction leakage currents can be minimized using F-doped HDP-CVD with HT-RTO. It was also confirmed that compressive stress in the F-doped HDP-CVD sample is smaller in every measurement point around STI than that in the conventional HDP-CVD sample by convergent-beam electron diffraction (CBED). The Si-F bonds in the oxide film play a very important role in stress reduction. By utilizing HT-RTO, Si-F bonds remain and make the SiO2 film in the trench coarse. This technique is a very promising 45 nm node STI scheme with high performance and high reliability.

0.15µm BiC-DMOS technology with novel stepped-STI N-channel LDMOS

We developed a state-of-the-art BiC-DMOS process using 0.15µm technology. High-voltage MOSFETs were embedded in our standard 0.15µm CMOS process with a 0.13µm high density NVM. More intelligent mixed signal devices can flexibly be realized by this technology. Moreover, the reliability of n-ch LDMOS is markedly improved by the novel structure of stepped-STI LDMOS.

Practical approaches to improve thermal SOA for smart power IC

In this paper, approaches to improve thermal SOA (T-SOA) of LDMOS have been presented. We show three important points for T-SOA based on experimental data. Firstly, improvement of thermal stability, which is expressed by simple index “α”; a ratio of drain current at 200°C divided by that at 25°C. Secondly, suppression of parasitic NPN action that causes device destruction and the correlation between failure energy and off-state leak current is studied. Thirdly, reduction of the thermal impedance. We examined an effect of Cu plate on wafer surface and a thinning effect of wafer thickness, and found thinner wafers were quite effective for long pulse energy.

Enhanced active protection technique for substrate minority carrier injection in Smart Power IC

In this paper, protection techniques against parasitic action due to minority carrier injection into substrate for Smart Power ICs have been presented. We investigated the protection efficiency of active type protection for various layout arrangements that are applicable to realistic IC, and found that the protection efficiency was strongly dependent on the layout. We propose the active type protection structure at collector side, which is effective at avoiding interferences from other components in realistic IC. We also found that separate type protection, which is one variation of the collector side protection, is more effective. The area penalty and the dependence of protection efficiency on temperature were also discussed.

Evolution of Ion Implantation Technology and its Contribution to Semiconductor Industry

Industrial aspects of the evolution of ion implantation technology will be reviewed, and their impact on the semiconductor industry will be discussed. The main topics will be the technology’s application to the most advanced, ultra scaled CMOS, and to power devices, as well as productivity improvements in implantation technology. Technological insights into future developments in ion‐related technologies for emerging industries will also be presented.

Formation of S/D-extension using boron gas cluster ion beam doping for sub-50-nm PMOSFET

Boron doping using gas cluster ion beam (GCIB) is implemented for formation of source/drain-extension (SDE) of pMOSFETs with sub-50-nm gate length. As compared with low energy ion implantation, GCIB is confirmed to produce steep profile of /spl sim/2.5 nm/decade without tail distribution. By simple replacement of low energy boron implantation with GCIB doping, about 20-nm improvement in short-channel effect and almost the same current drivability are obtained for pMOSFETs. Considering that conventional spike RTA and no offset space were used in the fabrication process, GCIB doping is considered to be promising technology for 45-nm node and beyond.

Analysis of Hot Carrier Degradation of Lateral Double-Diffused Metal–Oxide–Semiconductor under Gate Pulse Stress

The lateral double-diffused metal–oxide–semiconductor (LDMOS) transistor is one of the key elements of high-power devices. It is difficult to evaluate the degradation of an LDMOS at the required temperature range, because the self-heating effect of an LDMOS is too large for conventional evaluation in DC. In this paper, we report on the hot carrier degradation of an LDMOS under high-power operation, by investigating the LDMOS deterioration in the case that both the device structure and junction temperature (Tj) are different. The Tj of an LDMOS is controlled by operating the gate voltage (Vg) in pulse mode. Controlling Tj by operating Vg in pulse mode, the Tj dependence of hot carrier degradation under high-power operation can be evaluated widely and quantitatively. The threshold voltage (Vth) shift is observed according to the bias temperature mode irrespective of the device structure. On the other hand, the shift of drain current is affected by the length of the accumulation region under the gate electrode, and a relatively small increase in drain current (Ids) shift is observed with decreasing Tj. These phenomena are clarified from the results of charge pumping measurement and simulation.

Application of Cluster Boron Implantation to pMOSFETs

We applied B18HX+ as an alternation of B+ or BF2+ to the implantation for source‐drain extension in pMOSFETs corresponding to various technology nodes from 65 nm to 28 nm. We could obtain identical or better characteristics compared to the cases of conventional ions. In addition, we found from blank wafer that larger impact damage to Si atoms in B18HX+ implantation leads to more advantageous Rs‐Xj in activation processing with only MSA.

Advantages of B/sub 18/H/sub 22/ ion implantation and influence on PMOS reliability

In this paper, the impact of cluster ion (B/sub 18/H/sub x//sup +/) implantation on SDE formation are investigated in detail. It has been shown that B/sub 18/H/sub x//sup +/ ion implantation not only can make ultra-shallow junction for 45 nm node and beyond and but also has self-amorphization property and can reduce the channeling tail in the boron distribution without pre-amorphization implantation. In addition, B/sub 18/H/sub x//sup +/ ion implantation can be expected to reduce a fluctuation of MOSFETs, compared with B/sup +/ implantation. Cluster implantation is the reliability issue by hydrogen atom, because a large amount of hydrogen atoms are simultaneously introduced with boron into the silicon substrate. Moreover, neither the increase of junction leakage current nor influences of hydrogen which is introduced during B/sub 18/H/sub x//sup +/ implantation on PMOS reliability does not occur. The amorphization effect are evaluated by TEM observation and boron and hydrogen profiles by SIMS analysis.

A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond

2. Introduction Recently, stress-induced mobility enhancement has become one of important technologies, and various types of strains have been introduced in silicon devices [1]. On the other hand, it has been studied that mechanical stress originated from Shallow Trench Isolation (STI) leads to electron mobility degradation depending on transistor layout [2] and increase of junction leakage current caused by band-gap narrowing [3][4] as isolation pitch has been shrunk. Fig. 1 shows the dependence of drain current Id on the distance between channel and STI edge (drain side space Ld = source side space Ls). The Id of NMOS transistor is amazingly degraded as Ld(=Ls) is reduced, while PMOS transistor is less affected. It has been explained that the electron mobility is degraded by compressive stress induced by STI. In order to improve a device performance, it is necessary not only to introduce some new channel strain technique but also to control such a process-induced stress as STI. In this paper, we present the totally strain-controlled STI process using new gap-filling materials and following strain-controlled processes.