Takashi Ipposhi

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal gates and ion implantation for V/sub th/ control. The target V/sub th/ for low-power applications was achieved by using ion implantation for V/sub th/ control. We propose a 6-transistor SRAM memory cell in which we obtain even more benefit from the new device structure by adding a feedback mechanism. A proposed 6-Tr SRAM memory cell is shown to dramatically improve SNM characteristics at the 65-nm technology nodes, and this effect will also apply at finer nodes.

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET2RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility

Smallest V th variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate

A ldquosilicon on thin BOXrdquo (SOTB) CMOS with a 50-nm single metal (FUSI) gate has been developed. By employing an intrinsic channel and a metal gate, this SOTB achieves the smallest Vth variability ever reported. The measured Pelgrom coefficients of the SOTB were 1.8 and 1.5 for NMOS and PMOS, respectively, even in the case of relatively thick EOT of 1.9 nm. Both multi-Vth control as well as suppression of short-channel effects were carried out simply by adjusting the impurity concentration beneath the BOX layer while keeping the channel almost intrinsic. Inverter delay and off-current were optimized by controlling gate-overlap length by means of a dual-layer offset spacer. It is shown that, within planar-type low-power CMOS devices, the SOTB is the most scalable because of its capability of multi-Vth and excellent matching characteristics.

Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure including connections of the access and the driver transistors bodies to the word line is proposed to realize low-voltage operation. We developed the direct body contact technology to apply forward biases to the bodies without area penalties and increases of parasitic gate capacitances by using the hybrid trench isolation for the first time. Moreover, the standby current does not change because the body bias is not applied when the word-line voltage is low level. It is successfully demonstrated that low-voltage and high-speed operation is achieved by using the ABC SOI SRAM.

An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

An idea for obtaining unique identification (ID) numbers using polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a logic LSI compatible process is proposed. Like an actual human fingerprint, the characteristic variations of poly-Si TFTs are utilized for ID numbers in LSIs. The variation of poly-Si TFT characteristics is random, and this method offers unique, nonalterable, and nonduplicable numbers without any special processes, unlike other methods such as flash memory and mask ROM. These characteristics are highly suitable for ID number applications. The device physics of poly-Si TFTs for realizing the stable recognition of ID numbers was studied and a recognition circuit is proposed. The design guidelines for the grain size of poly-Si and AFD applications are also discussed.

Controllable Inverter Delay and Suppressing V th Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture

45 nm-gate SOTB (silicon on thin BOX) technology for LSTP application has been successfully developed. In the SOTB device, short-channel effect immunity without channel doping and back-gate bias threshold voltage (Vth) control are demonstrated. GIDL is reduced with avoiding drive current and inverter delay degradation minimum by optimizing offset source/drain extension to gate overlap. We have also proposed the SOTB device design enabling the controllable inverter delay and low Vth fluctuation for logic and SRAM memory cell transistors. Inverter delay can be improved from 19.3 to 10.5 ps by applying the forward back-gate bias. Furthermore, Vth fluctuation can be reduced about 16% by applying the reverse back-gate bias. A 6-transistor SRAM memory cell of the SOTB structure by adding a reverse back bias control has shown to dramatically improve SRAM memory cell stability.

Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode

A fully depleted silicon-on-insulator (FD SOI) device having an ultrathin buried oxide (BOX) with a 45-nm fully silicided (FUSI) NiSi gate, and a hybrid SOI/bulk complementary metal oxide semiconductor (CMOS) integration process have been developed. The optimal threshold voltage (Vth) for low stand-by power (LSTP) applications in FUSI gate silicon on thin BOX (SOTB) MOSFETs was achieved while keeping a lightly doped channel. By using back-gate bias, we have demonstrated the optimization of device power and performance and a reduction in Vth variation after device fabrication. We have also shown that the characteristics of the integrated hybrid bulk transistor are comparable to those of conventional bulk transistors.

A 0.05×0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory

An ultra-small RFID chip uses an electron beam for writing 1T memory cells. A 90nm SOI CMOS process and double-surface electrode chip structures enable the design of 0.05times0.05mm2 and 5mum-thick RFID chips with small, low-cost and highly-reliable 128b ID-memory. The chip is verified at a carrier frequency of 2.45GHz with measured communication distance of 300mm.

Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM

This paper presents an SOI-SRAM design employing a bootstrap scheme for ultra low voltage operation. The active body-biasing control (ABC) with PD-SOI is a key idea to enhance the boosting effect owing to a strong capacitive coupling. Our ABC-bootstrap scheme enables boosting the word line (WL) voltage higher than the supply voltage in short transition time without dual power supply rails. Simulation results have shown improvement in both the access time and operation at ultra low supply voltage less than 0.5V

A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

This paper presents that advanced actively body-bias controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of static noise margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs are improved by the advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32nm and 49% for 22nm node. It is summarized that this technology is one of countermeasures for emerging generations.