Yuuichi Hirano

Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSIs. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF/analog applications

For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved around 7% by changing the buried oxide (BOX) thickness from 400 nm to 150 nm because the self-heating effect is suppressed, and is improved around 5% by changing the substrate resistivity from 10 /spl Omega/cm to 1000 /spl Omega/cm because the power loss is reduced. In this work, the wafer engineering which consists of 1) <100>-channel, 2) optimization of BOX, and 3) high resistivity substrate, is proposed to improve the RF performance of the CMOSFET.

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.

High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices

It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18 /spl mu/m SOI 4 Mbit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13 /spl mu/m node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.

Bulk-layout-compatible 0.18-/spl mu/m SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Partial-trench-isolated (PTI) 0.18-/spl mu/m SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM were obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint.