K. Rim

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

Transconductance enhancement in deep submicron strained Si n-MOSFETs

We report the first measurements on deep submicron strained-Si n-MOSFETs. In spite of the high channel doping and vertical effective fields, electron mobility is enhanced by /spl sim/75% compared to typical MOSFET mobilities. The extrinsic transconductance is increased by /spl sim/45% for channel lengths of 0.1 /spl mu/m, when AC measurements are used to reduce self-heating effects. The improved transconductance demonstrates the use of strain-induced enhancements in both mobility and high-field transport to increase the average electron velocity, while maintaining the channel doping required to suppress short channel effects.

Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs

The strain dependence of the hole mobility in surface-channel p-MOSFETs employing pseudomorphic, strained-Si layers is reported for the first time. The hole mobility enhancement is observed to increase roughly linearly with the strain as the Ge content in the relaxed Si/sub 1-x/Ge/sub x/ buffer layer increases. When compared to the device with x=0.1, the devices with x=0.22 and 0.29 exhibit hole mobility enhancement factors of 1.4 and 1.8, respectively. In spite of the high fixed charge in our gate oxides, the device with Ge content x=0.29 still exhibits a mobility 1.3 times that of bulk Si MOSFETs with state-of-the-art oxides. The first measurements of the transconductance enhancements in submicron strained-Si p-MOSFETs are also reported.

Comparison of Si/Si1−x−yGexCy and Si/Si1−yCy heterojunctions grown by rapid thermal chemical vapor deposition

Abstract The materials and electronic properties of Si/Si 1− x − y Ge x C y and Si/Si 1− y C y heterojunctions grown by rapid thermal chemical vapor deposition are compared. Substitutional carbon incorporation is readily achieved in Si 1− x − y Ge x C y alloys by the addition of a carbon precursor such as ethylene or methylsilane during growth, using germane and dichlorosilane as the germanium and silicon sources respectively. In contrast, a significant fraction of the carbon is not substitutional in Si 1− y C y films grown using dichlorosilane in combination with either carbon source. A highly reactive silicon source, such as silane, enables the growth of high quality Si 1− y C y . Good agreement between the substitutional carbon concentration extracted from X-ray diffraction and the total carbon concentration measured by secondary ion mass spectrometry is observed in Si 1− y C y alloys grown at 550°C with silane, for carbon contents up to about 1.8 at.%. Si/Si 1− x − y Ge x C y and Si/Si 1− y C y metal-oxide-semiconductor capacitors show well-behaved electrical characteristics. Analysis of the capacitance-voltage data indicates that the band offsets are primarily in the valence band for Si/Si 1− x − y Ge x C y and the conduction band for Si/Si 1− y C y heterojunctions. The conduction band is lowered as carbon is added to Si and the effect is larger than expected from strain alone.

Measurement of the conduction band offsets in Si/Si1−x−yGexCy and Si/Si1−yCy heterostructures using metal-oxide-semiconductor capacitors

Metal-oxide-semiconductor (MOS) capacitors fabricated on in situ doped n-type Si/Si1−x−yGexCy and Si/Si1−yCy epitaxial layers were used to study the conduction band offsets in these heterojunctions. The heterostructures were grown epitaxially in a rapid thermal chemical vapor deposition reactor. Si/Si1−x−yGexCy samples with a nominal Ge concentration of 20 at. % and carbon fractions up to 1.3 at. % were studied. Carbon fractions up to 1.6 at. % were studied for the Si/Si1−yCy samples. Gate oxides were formed by thermal oxidation of the Si cap at 750 °C. X-ray diffraction measurements confirm that the processing did not affect the strain in the layers. Devices exhibit well-behaved high frequency and quasistatic capacitance–voltage (C–V) characteristics indicating the high electronic quality of the material. Capacitance–voltage measurements performed over a range of temperatures were used to extract the band offsets. Confinement of electrons at the heterointerface is apparent in the C–V curves of the Si/Si1...

Evaluation of the valence band discontinuity of Si/Si/sub 1-x/Ge/sub x//Si heterostructures by application of admittance spectroscopy to MOS capacitors

In this study, admittance spectroscopy is applied for the first time to MOS capacitors fabricated on Si/Si/sub 1-x/Ge/sub x//Si double-heterostructures, in order to evaluate the valence band discontinuity /spl Delta/E/sub v/ at the Si/Si/sub 1-x/Ge/sub x/ interface. The principle of the measurement is presented and verified by the experimental results. A new feature of admittance spectroscopy applied to MOS capacitors is the ability to select the interface whose barrier is measured, by controlling the gate voltage. This fact is confirmed by the measurement of MOS capacitors, which include a SiGe well with different Ge contents at the front and the back interfaces. It is found from this measurement that, while /spl Delta/E/sub v/ at the back interface of the double-heterostructure is measured under slight depletion conditions for MOS capacitors, /spl Delta/E/sub v/ averaged between the front and the back interfaces is measured under accumulation conditions. The Ge/sub x/ content dependence of the measured /spl Delta/E/sub v/ is found to be in fairly good agreement with the theoretical values.

Admittance spectroscopy analysis of the conduction band offsets in Si/Si1−x−yGexCy and Si/Si1−yCy heterostructures

Schottky diodes fabricated on in situ doped n-type Si/Si1−x−yGexCy/Si heterostructures grown by chemical vapor deposition were used for admittance spectroscopy in order to study the impact of carbon on the conduction band offsets. Samples with a nominal Ge concentration of 20 at. % and carbon fractions up to 1.3 at. % were studied. In these experiments, the measurement frequency was swept continuously from 1 kHz to 5 MHz, and the temperature was scanned in small increments from 20 to 300 K. Admittance signals in these samples were found to originate from three sources, namely doping freeze-out, band offsets, and traps. Signals arising from the band offsets indicate a conduction band edge lowering for Si/Si1−x−yGexCy of ∼33±22 meV/at. % C. A trap-related admittance signal at an energy of 228±25 meV below the Si conduction band was observed in the Si1−x−yGexCy sample with the highest C fraction (1.3 at. %). The trap energy measured by admittance spectroscopy is in close agreement with the activation energy ...

METAL-OXIDE-SEMICONDUCTOR CAPACITANCE-VOLTAGE CHARACTERISTICS AND BAND OFFSETS FOR SI1-YCY/SI HETEROSTRUCTURES

Metal–oxide–semiconductor (MOS) capacitors were fabricated on in situ doped n- and p-type Si1−yCy/Si heterostructures grown on Si substrates by chemical vapor deposition. Strained Si1−yCy epitaxial layers with substitutional carbon contents up to 1.6% were studied. High frequency and quasistatic capacitance–voltage (C–V) measurements exhibit well-behaved MOS characteristics, indicating high electronic material quality. Band alignments were extracted from MOS C–V measurements and one-dimensional device simulations performed over a range of temperatures. The conduction band energy of strained Si1−yCy is lower than that of Si by approximately 65 meV for 1 at. % carbon, while the valence band shows negligible offset to Si valence band.

Characteristics of Surface-Channel Strained Si 1-y C y n -MOSFETS

The first demonstration of n -MOSFETs fabricated using strained Si 1-y C y surface channels is reported. Tensile-strained Si 1-y C y layers with substitutional carbon contents up to 0.8 atomic percent were epitaxially grown on Si substrates by rapid thermal chemical vapor deposition, using silane and methylsilane as the silicon and carbon precursors. n -MOSFETS were fabricated using standard MOS processing with reduced thermal exposure to minimize the possibility of strain relaxation. A remote plasma CVD oxide was employed to form the gate oxide. The Si 1-y C y devices exhibit electrical characteristics that are typical for Si n -MOSFETs, with good turn-on and subthreshold characteristics. MOS capacitance-voltage analysis demonstrates comparable oxide interface qualities for the Si 1-y C y and Si control devices. No carbon-related leakage current is observed in source and drain diode junctions. Characterization of the MOSFET electron inversion layer mobility at room temperature shows comparable mobilities, within the sensitivity of the measurement, for the Si 1-y C y and Si control devices. This is in contrast to the mobility enhancement observed in n -MOSFETs fabricated using tensile- strained Si grown on relaxed Si 1-x Ge x layers. At low temperatures, the inversion layer mobility of Si 1-y C y devices is lower than that of the Si controls, and appears to be affected by Coulomb and possibly random alloy scattering.