J. Welser

Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors

The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors

Enhanced performance is demonstrated in n-type metal-oxide-semiconductor field-effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si/sub 1/spl minus/x/Ge/sub x/. Standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si. Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si. Similar enhancements are observed in the device transconductance. In addition, buried channel devices show peak room temperature mobilities about three times that of control devices.<<ETX>>

Strain dependence of the performance enhancement in strained-Si n-MOSFETs

The first measurements of the strain dependence of the electron mobility enhancement in n-MOSFETs employing tensilely-strained Si channels are reported. For pseudomorphic Si films grown on relaxed-Si/sub 1-x/Ge/sub x/ layers, the mobility enhancement ratio is found to saturate at approximately 1.76 at room temperature for x on the order of 0.20. As the temperature is lowered, the mobility enhancements for all strain levels initially converge, and subsequently decrease, with no enhancement observed at cryogenic temperatures (/spl ap/5 K). Similar behavior is seen at higher drain fields in the device transconductance.<<ETX>>

Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs

The strain dependence of the hole mobility in surface-channel p-MOSFETs employing pseudomorphic, strained-Si layers is reported for the first time. The hole mobility enhancement is observed to increase roughly linearly with the strain as the Ge content in the relaxed Si/sub 1-x/Ge/sub x/ buffer layer increases. When compared to the device with x=0.1, the devices with x=0.22 and 0.29 exhibit hole mobility enhancement factors of 1.4 and 1.8, respectively. In spite of the high fixed charge in our gate oxides, the device with Ge content x=0.29 still exhibits a mobility 1.3 times that of bulk Si MOSFETs with state-of-the-art oxides. The first measurements of the transconductance enhancements in submicron strained-Si p-MOSFETs are also reported.

Evidence of real-space hot-electron transfer in high mobility, strained-Si multilayer MOSFETs

New phenomena are reported in N-MOSFETs with high-mobility, strained-Si electron channels. A parasitic bipolar breakdown is observed at anomalously low drain voltages at reduced temperatures (<100 K) in devices with strained-Si channels buried beneath a relaxed-Si/sub 1-x/Ge/sub x/ capping layer. This breakdown is consistent with a mechanism involving real-space hot-electron transfer and hole confinement in the heterostructure, and is shown to be quenched by the addition of a surface strained-Si layer. This additional Si layer also offers the practical advantage of extending device performance enhancements to higher gate voltages at room temperature.<<ETX>>

Evaluation of the valence band discontinuity of Si/Si/sub 1-x/Ge/sub x//Si heterostructures by application of admittance spectroscopy to MOS capacitors

In this study, admittance spectroscopy is applied for the first time to MOS capacitors fabricated on Si/Si/sub 1-x/Ge/sub x//Si double-heterostructures, in order to evaluate the valence band discontinuity /spl Delta/E/sub v/ at the Si/Si/sub 1-x/Ge/sub x/ interface. The principle of the measurement is presented and verified by the experimental results. A new feature of admittance spectroscopy applied to MOS capacitors is the ability to select the interface whose barrier is measured, by controlling the gate voltage. This fact is confirmed by the measurement of MOS capacitors, which include a SiGe well with different Ge contents at the front and the back interfaces. It is found from this measurement that, while /spl Delta/E/sub v/ at the back interface of the double-heterostructure is measured under slight depletion conditions for MOS capacitors, /spl Delta/E/sub v/ averaged between the front and the back interfaces is measured under accumulation conditions. The Ge/sub x/ content dependence of the measured /spl Delta/E/sub v/ is found to be in fairly good agreement with the theoretical values.

Temperature and scaling behavior of strained-Si N-MOSFET's

Summary form only given. The device characteristics of N-MOSFETs fabricated in strained-Si have been investigated as a function of temperature and gate length. It is found that the low field mobility is enhanced compared to Si control devices at temperatures down at 20 K. For moderate fields, g/sub m/ is enhanced at all measured temperatures, for effective gate lengths down to 0.8 mu m (L/sub drawn/=1.5 mu m). At high power density, however, the devices exhibit a negative differential output resistance. The thermal conductivity of the relaxed Si/sub 1-x/Ge/sub x/ buffer layers is estimated by fitting polysilicon resistor characteristics to a first order model. >

Importance of inter-valley phonon scattering on mobility enhancement in strained Si MOSFETs

It has recently been reported that strained Si MOSFETs fabricated with relaxed SiGe layer exhibit very high mobility at room temperature, almost twice as high as that in conventional Si MOSFETs. While strained Si MOSFETs, compatible with Si LSI technology, are promising as the devices for the high speed, room temperature applications, the understanding of the carrier transport in strained Si is still lacking. In order to clarify the mechanism of the mobility enhancement, calculations of the subband structure and phonon-limited mobility in the inversion layer of strained Si were performed for the first time, compared with the calculations for the inversion layer of unstrained (conventional) Si. The effect of the band splitting due to strain was successfully incorporated in the subband calculation. It is demonstrated that the suppression of inter-valley phonon scattering is essential to the mobility enhancement in strained Si MOSFETs.