Ka Fai Chang

Heterogeneous 2.5D integration on through silicon interposer

Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (<1 mm separation) compared with several centim...

77-GHz Automotive Radar Sensor System With Antenna Integrated Package

In this paper, a 3-D integrated 77-GHz automotive radar front-end is presented. Embedded wafer level packaging (EMWLP) technology is proposed to eliminate the use of wire bonding, which not only introduces significant radio frequency loss, but also occupies large footprint for high-pin count die. The transceiver bare die is embedded in a reconfigured molded wafer with compression molding process. Double-sided multiple redistribution layers are formed to fan-out the transceiver input/output signals and through mold via is employed to realize the vertical interconnection. With these promising features, the EMWLP technology can be extended to a 3-D integration. A substrate integrated waveguide slot antenna is integrated on top of the EMWLP module and a lens is used to enhance the antenna directivity. The performance of the fully integrated radar front-end is tested and the measurement results show good package performance with RF loss around 5 dB for most of the samples. Temperature cycling reliability test was also performed by letting the fully integrated prototype goes through 1000 temperature cycles with JEDEC standard. The measured package loss spread across samples after 1000 cycles of TC test is about 13 dB, which is mainly due to the antenna warpage affecting the RF paths signal integrity.

Self-Shielded Circularly Polarized Antenna-in-Package Based on Quarter Mode Substrate Integrated Waveguide Subarray

A self-shielded antenna-in-package (AiP) covering IEEE 802.11a band is proposed in this paper, and the antenna is designed using quarter mode substrate integrated waveguide (QMSIW) subarray technology. Electromagnetic interference (EMI) in a system-in-package integrated with AiP is discussed firstly. Electric field distribution of the proposed AiP is simulated, and it shows that the metallic via-holes array in the QMSIW subarray approximates to the electric wall to isolate the electromagnetic field coupling and then to increase the EMI shielding. The operating principle of the proposed antenna is investigated through an isosceles right triangular waveguide. An antenna prototype is fabricated and measured. The measured results match with the simulated and analyzed results very well. It is demonstrated that the proposed QMSIW subarray with metallic via-holes array gives an attractive and promising way to design the AiP with self-shielded property.

An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs.

Study of transmission line performance on through silicon interposer

The high frequency performance of different types of transmission line structures (including microstrip line, coplanar waveguide, grounded coplanar waveguide and differential coplanar waveguide) fabricated on through silicon interposer (TSI) is studied and characterized experimentally up to 40 GHz in this paper. Design considerations and tradeoffs are discussed in order to realize low loss, high bandwidth interconnects on TSI for radio frequency and/or millimeter wave system integration. Experimental results reveal that all the designed transmission line structures have insertion loss of less than 0.56 dB/mm for frequencies up to 40 GHz. Good impedance matching over broad frequency range (till 40 GHz) is also achieved with return loss of greater than 15 dB. Additionally, for the differential coplanar waveguide structure, high isolation of more than 27 dB for frequencies up to 40 GHz is observed between the differential and common mode conversion.

Low Loss Suspended Membrane on Low Resistivity Silicon and Its Applications to Millimetre-Wave Passive Circuits

This paper presents the fabrication process of a thin suspended membrane on normal low resistivity silicon (LRSi), which is then utilized to design millimeter-wave (mm-wave) transmission line and passive circuits with low loss. First, two redistribution metal layers are formed on a plain LRSi wafer with benzocyclobutene in-between. Then, the wafer is thinned down and etched from backside with a specific pattern. Based on this process, a volume is introduced underneath the front side structure and the lossy LRSi substrate is replaced by air, which is the ideal substrate with no loss. Using this method, the substrate loss that contributes the majority part of total loss in mm-wave circuits on LRSi is eliminated. As the operating frequency goes into mm-wave region, the circuit size is scaled down so that the suspended portion is so small that it will not increase the mechanical instability of the structure. Therefore, the proposed suspended membrane on LRSi technology provides an excellent platform to construct mm-wave components. A U-shaped slotline resonator formed on the first redistribution layer is proposed and its quality factors are studied in detail. A second-order bandpass filter is designed and implemented by cascading two such U-shape slotline resonators. The measured frequency responses exhibit good filtering performance, with fractional bandwidth of 13.9% at 126.8 GHz, midband insertion loss of 3.9 dB and passband return loss larger than 14.2 dB. It demonstrates that the proposed suspended membrane on LRSi technology is an excellent candidate for designing low loss mm-wave components.

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration.

Electrical transmission characteristics of vertical transition with through silicon vias (TSVs) in 3D die stack

Two vertical transitions with through silicon vias (TSVs) in 3D die stack are designed and their high frequency electrical characteristics are presented in this paper. The two vertical transitions consist of TSVs for obtaining electrical connection between the die front side and back side. Back side redistribution layer is eliminated in the designs to simplify the fabrication process without sacrificing the electrical performance. Design considerations and guidelines are provided to design high speed TSV structure up to 50 GHz. Different kinds of transmission line interconnects (for instance, microstrip line and coplanar waveguide) are implemented at the input/output extensions for different applications. For both vertical transition designs, the simulated insertion loss is better than 0.65 dB up to 50 GHz while good impedance matching from DC to 50 GHz is obtained with the simulated return loss greater than 14 dB.

Investigation of vertical interposers for high frequency operation

Horizontal probe station poses challenges in determining performance of vertical interposers for test socket. In this paper, a PCB test structure has been proposed for measurement of our designed interposers up to 20 GHz. A new test structure is further proposed and simulated with HFSS to achieve a higher operating frequency. By converting the S-parameters of test structures to T-parameters and splitting of cascaded blocks using optimization method, the performance of an individual vertical interposer can be obtained.

High bandwidth interconnect design opportunities in 2.5D Through-Silicon interposer (TSI)

Silicon interposer technology enables the integration of multiple silicon dies on it providing fine pitch interconnects for die-to-die communication and Through-Silicon Vias (TSVs) for package/PCB level connections. Therefore, this technology has been identified as a viable solution for logic and memory types of applications where higher bandwidth in required. In the paper, we characterize thick (t=3μm; w/s=3μm/3μm) as well as thin (t=1μm; w/s=2μm/2μm) front side die-to-die Cu interconnects along with chip-to-substrate interconnects containing Through-Silicon Vias (TSVs) and estimate the data transfer capabilities of them. Evaluation of digital signal interconnect performance shows that the maximum bandwidth requirements expected by the latest memory technologies can be achieved by the silicon interposer technologies characterised in this paper.