Kaiping Liu

Fluorine-assisted super-halo for sub-50-nm transistors

The potential of using a fluorine-assisted super-halo for sub-50-nm transistors is analyzed for the first time. The capability of producing a super-sharp halo using fluorine is demonstrated by one-dimensional (1-D) SIMS profiles. The added ability to tailor the halo profile using fluorine for different transistor criteria on junction capacitance, tunneling current, V/sub t/ roll-off, and mobility is demonstrated. The impact of the resulting fluorine-assisted halo dopant profile on the transistor characteristics is evaluated using TCAD simulations. Experimental data show that the fluorine-assisted halo process results in lowered junction capacitance and improved I/sub on/-I/sub off/ characteristics for both nMOS and pMOS.

Improving manufacturing variability control in advanced CMOS technology by using TCAD methodology

Rapid development of a well controlled manufacturing process is a key component of marketplace success. Accomplishing this requires a thorough understanding of the effects of process variations on parametric yield. Use of Technology Computer Assisted Design (TCAD) simulations and statistical analysis can decrease the time needed to assess the manufacturability of various transistor design options, and identify the key process parameters that cause the largest variations. This paper covers a new methodology that combines Design of Experiments (DOE) with process and device simulations to generate transistor parametric statistical models. Monte-Carlo simulations are performed to generate transistor parametric sensitivities and statistical distributions. Examples of applying this methodology to 130nm technology will be given.

Improving device performance and process manufacturability through the use of TCAD

The use of TCAD as a powerful tool for improving device performance and process manufacturability is describe din this paper. The ability for TCAD simulation to provide quick insight and understanding to better pMOS heavy doped drain extension design is illustrated. The impact of surface dielectric property and interface condition on the HDD diffusion profile, the transistor performance, and the transistor parametric variation is discussed through the use of SIMS profiles, simulation results, and silicon dat. Significant changes in HDD profile, transistor characteristics and parametric variability are attributed to surface oriented dopant diffusion. The severity of such changes can vary with varying surface dielectric properties. Through TCAD simulations, we postulate that the surface oriented dopant diffusion is mainly due to the existence of a super steep interstitial gradient (SSIG), in addition to SPE dopant transport effects. Monte Carlo implant simulations using UT-Marlowe and SIMS profiles how that higher-energy-lower-dose HDD implant would produce a better HDD diffusion profile of same junction depth than lower- energy-higher-dose HDD implant does, as a result of SSIG. SIMS experiments designed to reduce surface oriented diffusion by using Ge and F co-implant are discussed. The SIMS profiles show that Ge is able to reduce surface oriented dopant diffusion by steric effects, but F co- implant produces the best HDD profile.