Manoj Mehrotra

A 65 nm CMOS technology for mobile and digital signal processing applications

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/mm/sup 2/ and a SRAM memory density of 1.4 Mb/mm/sup 2/ using a sub-0.49 /spl mu/m/sup 2/ bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

A 1.2V, sub-0.09 /spl mu/m gate length CMOS technology

CMOS technology for 1.2 V high performance applications is being scaled to sub-0.09 /spl mu/m physical nominal gate lengths and with effective gate dielectric thickness less than 2 nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09 /spl mu/m (post gate reoxidation), and gate dielectric thickness of 2.7 nm (nMOS), 3.0 nm (pMOS) (inversion at 1.2 V), nMOS and pMOS I/sub drive/ is 763 /spl mu/A//spl mu/m and 333 /spl mu/A//spl mu/m respectively, at 1.2 V with maximum I/sub off/=5 nA//spl mu/m. Gate-drain overlap in this work is /spl sim/210 /spl Aring//side and bottomwall junction capacitance is reduced to 0.8 fF//spl mu/m/sup 2/ (pMOS) and 1.1 fF//spl mu/m/sup 2/ (nMOS). With reduced parasitics and high drive current, the 1.2 V technology FOM (Figure-of-Merit) is >39 GHz, meeting the roadmap trend.

Improving device performance and process manufacturability through the use of TCAD

The use of TCAD as a powerful tool for improving device performance and process manufacturability is describe din this paper. The ability for TCAD simulation to provide quick insight and understanding to better pMOS heavy doped drain extension design is illustrated. The impact of surface dielectric property and interface condition on the HDD diffusion profile, the transistor performance, and the transistor parametric variation is discussed through the use of SIMS profiles, simulation results, and silicon dat. Significant changes in HDD profile, transistor characteristics and parametric variability are attributed to surface oriented dopant diffusion. The severity of such changes can vary with varying surface dielectric properties. Through TCAD simulations, we postulate that the surface oriented dopant diffusion is mainly due to the existence of a super steep interstitial gradient (SSIG), in addition to SPE dopant transport effects. Monte Carlo implant simulations using UT-Marlowe and SIMS profiles how that higher-energy-lower-dose HDD implant would produce a better HDD diffusion profile of same junction depth than lower- energy-higher-dose HDD implant does, as a result of SSIG. SIMS experiments designed to reduce surface oriented diffusion by using Ge and F co-implant are discussed. The SIMS profiles show that Ge is able to reduce surface oriented dopant diffusion by steric effects, but F co- implant produces the best HDD profile.

New methodology of simulating pocket-implanted sub-0.18-μm CMOS

This paper presents a new approach to model the pocket implanted transistors for simulating sub-0.18 micrometer CMOS. The simulation approach presented in the prior publications for pocket implanted transistors has limitations in accurately matching the experimental Vt-rolloff and DIBL characteristics for gate lengths in the sub-0.18 micrometer regime. This is due to the fact that the pocket profile used in the prior simulator does not account for the 2-D boron redistribution effect caused by the source/drain extension implant (MDD). The new model incorporates two-dimensional redistribution of pocket caused by the drain extension implant. There are no additional modeling parameters added for the simulations when compared to the previously published model. The calibrated simulator with the new pocket model shows good agreement with the experimental data for 0.10 - 0.18 micrometer technology transistors.

Prediction of deep submicron CMOS transistor performance and comparison with projected performance trends using tuned simulations

In this paper, a simulation study to predict the performance of CMOS technology in the deep sub-micron regime (0.20 micrometer down to 0.05 micrometer) is presented. The metric used to evaluate the CMOS transistor performance is a Figure of Merit (FOM). Using tuned process and device simulators, the performance FOM of bulk CMOS technologies were evaluated, with varying (1) gate lengths in the range of 0.05 - 0.20 micrometer, (2) power supply voltages (Vdd) of 1.0 - 1.8 V, (3) gate oxide thicknesses (Tox) of 20 - 40 A, (4) maximum off-state leakage currents of 0.01, 1 and 100 nA/micrometer, (5) different source/drain resistances and (6) different polysilicon doping levels. Vdd and Tox were scaled with gate length such that Vdd/Tox is fixed at about 5 MV/cm. It is found that it is increasingly difficult to keep the proportionality between performance FOM and 1/Lgate as the gate length is scaled to around 0.10 micrometer or below. This deviation is due to the decreasing trend of transistor drive current caused by the low supply voltages to be used and the nonscalability of VT. In order to try and improve the performance of CMOS technology, metal-gated Fully Depleted SOI CMOS transistors were evaluated in this study. It was found that although Fully Depleted Metal-Gate SOI provides an improvement in performance over conventional bulk CMOS technology, the FOM does not linearly scale with the gate length. The improvement in FOM obtained is almost entirely due to the smaller junction capacitance in SOI and not due to significantly increased drive currents in metal-gate FD-SOI when compared to conventional CMOS. Further, FOM performance falls short of the roadmap targets as the gate lengths are scaled below 0.10 micrometer just as in bulk CMOS. The effects of Off Current specifications and supply voltage on FOM were studied. It is shown that the CMOS performance can be improved by: (1) slightly increasing the supply voltage, and (2) using a dual- VT approach in which low-VT transistors are used in the critical path to improve circuit performance. With these approaches it is possible to extend the proportionality between FOM and 1/Lgate down to about 0.08 micrometer gate length.

Optimum junction depth design of the S/D extension regions (MDD) for sub-0.18 μm CMOS technologies

For scaled CMOS technologies, the source/drain-extension (MDD) junction depth (Xj) is important in achieving optimized device performance. According to the SIA roadmap, Xj is about 0.3 - 0.5 times the nominal gate length (Lgnom) for previous device generations as shown in Fig. 1. For devices with fixed Lgnom, shallower MDD can improve the short channel effects and the drive current sensitivity, however, trade-off occurs due to the increase in effective gate length and channel resistance. Various engineering techniques such as pocket implant can also change the requirement for Xj. It is therefore important to predict the Xj requirement for various transistor designs and facilitate faster turn-around time and minimize the design cost. In this work, a tuned 2-D MEDICI simulator is used to investigate the effect of Xj for 0.1 micrometer to 0.15 micrometer gate length devices. Effects of pocket implant and the use of an additional MDD spacer are compared. Both high performance (maximum off current equals lnA/micrometer) and low power (maximum off current equals 0.01nA/micrometer) devices are studied. For a given device design, an optimum Xj is found where the nominal drive current is maximized for fixed Lgnom and source/drain resistance (RSD). Key results are as following. (1) For high performance devices with pocket implant, the optimum Xj for S/D extension is approximately 300A (450A) for 0.1 micrometer (0.13 micrometer) Lgnom devices. Without pocket implant, the optimum Xj is reduced to approximately 250A (300A) which falls below the predicted lower limit of 0.3xLgnom. The improvement in the short channel roll-off by pocket implant allows the use of deeper junctions. Furthermore a 5% increase in nominal drive current is also observed for 0.1 micrometer devices with pocket implant. (2) The Xj requirement can be relaxed by using a thin MDD sidewall spacer. By adding a 200A MDD spacer, the optimum Xj for high performance device with pocket implant is approximately 450A and 550A for 0.1 micrometer and 0.13 micrometer node devices. However, addition of a MDD spacer will result in reduced gate overlap and hence larger RSD. It is found that a 200A spacer would result in an additional S/D resistance of 80 (Omega) for nMOS devices and cause 3 - 6% degradation in drive current. (3) For low power version devices with higher threshold voltage, Lgnom is adjusted to 0.11 micrometer and 0.15 micrometer while the minimum gate length (Lgmin) is set to be 85% Lgnom to account for the better short channel effects. The optimum Xj for low power devices with pocket implant is 250A (350A) for 0.11 micrometer (0.15 micrometer) Lgnom devices which is about 50 - 100A shallower than the Xj for high power devices. MDD spacer is more effective for low power devices and a 200A MDD spacer increases optimum Xj by 200A, matching the requirement for high power devices.

Prediction of CMOS transistor performance at 0.10-μm gate length using tuned simulations

Predictive device simulation is essential in order to improve MOSFET design, and reduce development time and costs. In this paper, the results of a simulation study carried out to predict the performance of N and P channel MOSFETs having a physical gate length of 0.10 micrometer at supply voltages of 1.2 and 1.5 V are presented. The study was used to determine the feasibility of the FOM goal for scaled 0.10 micrometer CMOS, and to identify the values of key device parameters [the external source drain resistance (Rext), poly-gate doping, etc.] which would improve device performance.

Sheet resistance requirements for the source/drain regions of 0.11-μm gate length CMOS technology

MOSFETs with partially contacted source/drain regions are often used in ASIC designs in order to improve the layout density of the gate arrays. Such contacting scheme adds resistance to current flow which reduces transistor current and hence degrades device performance. This paper presents the effect of source/drain region sheet resistance on the performance figure of merit (FOM) for partially contacted deep submicron CMOS transistors. These partially contacted transistors are modeled as distributed network of MOSFETs and resistances in order to study the impact of source/drain region resistance on drive currents. It is found that the source/drain sheet resistance plays a significant role in determining the FOM of these transistors. For example, our modeling shows that for 0.11 micrometer technology, a source/drain region sheet resistance of only 7 Ohms/sq. results in 1% degradation in performance FOM for diagonally contacted transistors with W/L of 20 and Ws of 0.27 micrometer.