Kaladhar Radhakrishnan

FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs

Intels® 4th generation Core™ microprocessors are powered by Fully Integrated Voltage Regulators (FIVR). These 140 MHz multi-phase buck regulators are integrated into the 22nm processor die, and feature up to 80 MHz unity gain bandwidth, non-magnetic package trace inductors and on-die MIM capacitors. FIVRs are highly configurable, allowing them to power a wide range of products from 3W fanless tablets to 300W servers. FIVR helps enable 50% or more battery life improvements for mobile products and more than doubles the peak power available for burst workloads.

A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors

We present a 100MHz eight-phase synchronous buck converter using air-core inductors. The voltage regulator (VR) chip was manufactured in a 90nm CMOS process and mounted on a flip-chip test package together with surface-mount inductors and decoupling capacitors. The measured peak efficiency is 84.0% for Vin/Vout= 2.4V/1.5V and 79.3% for 2.4V/1.2V. The VR delivers a load current of 12A in an area of only 25mm2 and 2.5mm height. This is the first demonstration of a high-frequency VR with air-core inductors, that reaches a record power density of 3.78kW/in3.

Full-wave analysis of multiconductor transmission lines on anisotropic inhomogeneous substrates

The full-wave analysis of the generalized microstrip line on an inhomogeneous anisotropic substrate is carried out by using the finite-difference method. The resulting sparse matrix equation is solved efficiently using the bi-Lanczos algorithm. The use of the inhomogeneous wave equation to formulate the problem makes it easy to analyze structures with multilayered substrates. The algorithm can analyze complicated structures with multiple conductors at arbitrary locations. A spatial interpolation scheme is used to evaluate the contribution from the off-diagonal terms in TT and T. The use of the bi-Lanczos algorithm allows us to solve the problem at O(N/sup 1.5/) complexity. Storage requirements can be made to scale as O(N). This makes it possible to analyze large problems on a small computer. Very good agreement is seen between published results and results obtained using this technique.

Microprocessor platform impedance characterization using VTT tools

This paper presents a method to extract the impedance profile of Intel processor platforms in frequency domain using custom, high di/dt electronic loads referred as VTT tools. Although currently followed time domain characterization yields the voltage response of the motherboard (MBD) to the current profile generated by the VTT tool, it does not directly provide the MBD impedance as a function of frequency. Without knowledge of the impedance profile it is difficult to fully understand the impact motherboard layout and decoupling capacitor filter configurations have on the overall power delivery system performance. Theory of the method, VTT tool modifications and platform waveform results discussed. Internally developed computer scripts that process the ratio of the measured voltage and current FFTs as the platform impedance over frequency are described. Correlation of simulation models is provided. Steps towards generalization of the method for maximum industry adoption are identified

Package Inductors for Intel Fully Integrated Voltage Regulators

Intel fourth-generation and fifth-generation Core microprocessors are powered by high-frequency integrated switching voltage regulators. The inductors required to implement these regulators are constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the construction of these inductors including representative results from production packages. Measured inductors reported in this paper span from 1 to 6.7 nH under 2.4 mm2 and achieve Q of up to 24 at 140 MHz (the switching frequency).

Characterization of discrete decoupling capacitors for high-speed digital systems

This paper describes frequency-dependent characterization of multi-terminal decoupling capacitors (2, 8, 14, and any arbitrary number of terminals) by using a full-wave tool developed at Intel. This tool can capture high frequency effects with fast CPU run time, which enables accurate modeling of the power delivery system. The full-wave S-parameters have been validated with the measurements and the modeled data obtained from a commercial tool (HFSS). Based on its fast and accurate solution, different design configurations of capacitors have been studied to identify the optimal configuration which maximizes the performance of the decoupling capacitor. To capture the frequency-dependent behavior of capacitor impedance, a higher order representation made up with 7 or 9 elements of RLGC was developed. This circuit representation was used to assess the accuracy of the conventional series lumped RLC capacitor model. Finally, the responses were incorporated into a high performance microprocessor power delivery network to investigate system performance.

A compact 802.11 a/b/g/n WLAN Front-End Module using passives embedded in a flip-chip BGA organic package substrate

This paper discusses the design and implementation of a compact RF Front-End-Module for 802.11a/b/g/n application. A high performance embedded passives technology has been developed by extending existing multilayer FCBGA packaging substrate technology to include thin film capacitors, resistors and spiral inductors. Using these basic elements, all of the passive building blocks for the RF front-end module (FEM) have been designed and characterized individually. Several of these building blocks have then been used in combination with surface mounted active dies to realize a dual-band one-transmit/one-receive WiFi FEM with dimensions of 8 mm × 8mm × 1mm. Preliminary measurements indicate small signal gain of 10dB at 2.4 GHz for the Rx chain

Package embedded inductors for integrated voltage regulators

Intel® 4th generation Core™ microprocessors are powered by high frequency integrated switching voltage regulators. The inductors required to implement these regulators were constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the simulation and measurement of these embedded inductors including representative results from production packages.

Integrated modeling methodology for core and I/O power delivery

Traditionally core power delivery and I/O signal analysis were performed separately to analyze the performance of a microprocessor package. The coupling between I/O and core power delivery was assumed negligibly small. In this paper, we describe a methodology to for analyzing core and I/O power delivery using the same integrated model. Having an integrated model allows us to study the noise induced on the core power nets due to switching currents on the I/O nets and vice-versa. Having an integrated model also gives us the opportunity to study the relative merits of separating or combining the core and I/O power networks.

Embedded capacitors in the next generation processor

Embedded passives technology has been of interest to electronic package designers for performance improvement and package size reduction. With the explosion of mobile phones, tablets and other hand held devices, the need for smaller form factor products with equivalent or better electrical performance makes a very compelling case for embedding passives. The benefits of embedded passives are not limited to small form factor devices. Larger die and server products requiring high performance power delivery solutions can also benefit substantially from embedded capacitors. Intel in collaboration with its suppliers has developed and commercialized a disruptive embedded capacitor technology that provides significant power delivery benefits for high performance computer applications. This is the first commercialized embedded capacitor technology used by Intel.