Jerry D. Hayes

Process and environmental variation impacts on ASIC timing

With each semiconductor process node, the impacts on performance of environmental and semiconductor process variations become a larger portion of the cycle time of the product. Simple guard-banding for these effects leads to increased product development times and uncompetitive products. In addition, traditional static timing methodologies are unable to cope with the large number of permutations of process, voltage, and temperature corners created by these independent sources of variation. In this paper we will discuss the sources of variation; by introducing the concepts of systematic inter-die variation, systematic intra-die variation and intra-die random variation. We will show that by treating these forms of variations differently, we can achieve design closure with less guard-banding than traditional methods.

Fast Characterization of Threshold Voltage Fluctuation in MOS Devices

Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage (VT) of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch in MOS devices. Our VT scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage VGS for a fixed drain current IDS and drain-to-source voltage VDS . We present circuit schematics to characterize VT scatter by measuring VGS variation for a large set of devices arranged in an individually addressable array. We report experimental results of VT scatter measurement from test chips fabricated in 65-nm silicon-on-insulator and 65-nm bulk CMOS processes. We also measure and report the magnitude of local device current mismatch caused by VT fluctuation.

Rapid Characterization of Threshold Voltage Fluctuation in MOS Devices

We present a technique for fast characterization of random threshold voltage variation in MOS devices. Our Vtau scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage VGS for a fixed drain current IDs and drain-to-source voltage VDS. We measure VGS variation for a large set of devices arranged in an individually addressable array and report results of Vtau scatter measurement from a test chip in a 65 nm SOI CMOS process. We also measure and report the magnitude of local device current mismatch caused by the Vtau fluctuation.

Yield estimation via multi-cones

We propose a new yield estimation algorithm which estimates the acceptability region as the union of spherical cones. The algorithm works by dividing the input parameter space into approximately equi-probable cones, efficiently estimating the refined weight contributions for each cone, then combining the results to get the total yield. The algorithm is broadly similar to the worst-case-distances method, but is more generally applicable for cases with - for example - multiple failure regions. The algorithm is quite accurate, and offers several orders (>;100×) of magnitude of speedup compared to traditional Monte Carlo. The paper includes example applications to difficult high-yield circuits like SRAM.

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations

Fast changing power distribution systems request a dynamic system configuration capability of reacting to volatile consumption demands in an economical way. Load balancing in power distribution systems is an essential technique for smart grid that enables reliable electricity delivery to end customers. This paper is the first work focusing on load balancing using switch reconfiguration, tie-line addition, and wire upgrade simultaneously, while existing works adopt only one of the three techniques to configure the power distribution system. We observe that the new load balancing problem induces a new challenge, dynamic topology rotation, which cannot be handled by existing solutions. To overcome this challenge, we first consider bidirectional power flows and formulate the load balancing problem as a mixed-integer quadratically constrained quadratic program (MIQCQP). To reduce the computational complexity, it is further transformed into a mixed-integer linear program (MILP) without loss of optimality. Experimental results show that, on real power distribution networks, our approach produces optimal solutions that are unlikely to be found in ad-hoc heuristics methods.

Applying VLSI EDA to energy distribution system design

Energy distribution networks refer to that part of the electricity network that delivers power to homes and business. It is reported that significant amounts of energy are being wasted simply due to inefficiencies in this network. Further, this domain is rapidly changing with new types of loads such as electric vehicles or the spread of new types of energy sources such as photo-voltaic and wind. In this paper, we demonstrate a comprehensive design automation capability for energy distribution networks leading to much more flexible yet effective system. The new systems capabilities include power load distribution and transfers, equipment upgrading, geospatial-aware network optimization, outage identification, contingency planning and loss analysis/reduction. These features are enabled by advanced simulation, analysis and optimization engines that are adapted from those available in the traditional VLSI design automation area. The paper will conclude with potential future research directions that require further innovations in energy distribution networks.

Rapid characterization of parametric distributions using a multi-meter

We present a technique for fast characterization of the statistical mean and sigma of parametric variations. The technique uses a scan chain to sequentially cycle through a device array, creating a periodic waveform that can be directly measured using a multi-meter. The DC and RMS values of the waveform directly give the mean and sigma of the parameter distribution. We show the technique is sufficiently general and can be applied to wide range of characterization strategies. A VTH characterization array was implemented in a 65 nm bulk CMOS process where we compare traditional individual device measurements for calculating statistics with the direct mean and sigma measurement technique using the multi-meter.

In-situ measurement of variability in 45-nm SOI embedded DRAM arrays

A technique for in-situ measurement of process variation in deep trench capacitance, bitline capacitance, and device threshold voltage in embedded DRAM arrays is presented. The technique is used to directly measure the parameter statistics in two product representative 45-nm SOI eDRAM arrays.

Nonlinear circuit solver with linear interconnect load

We consider a current source driver macromodel approach for the fast solution of a combined on-chip driver-interconnect model problem. In this approach, we divide the problem into two separate parts which are solved independently so that the nonlinear solution is only required for a small portion of the overall problem.

Solver for current source type driver(s) and interconnect with linear or nonlinear loads

Current source type models are widely used for noise and timing analysis of on-chip drivers and interconnects. A time domain solution using Spice may be too time consuming. Here, we consider small solver for nonlinear driver(s) with interconnects and linear or nonlinear loads.