Kanji Oishi
Hitachi
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Publication
Featured researches published by Kanji Oishi.
IEEE Journal of Solid-state Circuits | 1991
Kunio Uchiyama; Hirokazu Aoki; Osamu Nishii; Susumu Hatano; Osamu Nagashima; Kanji Oishi; Jun Kitano
The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 mu m CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic. >
Archive | 1992
Osamu Nishii; Kunio Uchiyama; Hirokazu Aoki; Kanji Oishi; Jun Kitano; Susumu Hatano
Archive | 1995
Ken Shibata; Kanji Oishi
Archive | 1992
Katsuyuki Sato; Tadahiko Nishimukai; Kunio Uchiyama; Hirokazu Aoki; Susumu Hatano; Kanji Oishi; Hiroshi Fukuta; Takashi Kikuchi; Yasuhiko Saigou
Archive | 1989
Kunio Uchiyama; Hirokazu Aoki; Susumu Hatano; Kanji Oishi; Takashi Kikuchi; Hiroshi Fukuta; Yasuhiko Saigou
Archive | 1989
Katsuyuki Sato; Tadahiko Nishimukai; Kunio Uchiyama; Hirokazu Aoki; Susumu Hatano; Kanji Oishi; Hiroshi Fukuta; Takashi Kikuchi; Yasuhiko Saigou
Archive | 1996
Atsuko Momma; Miki Matsumoto; Kanji Oishi
Archive | 1993
Takayuki Kawahara; Masakazu Aoki; Yoshinobu Nakagome; Makoto Hanawa; Kunio Uchiyama; Masayuki Nakamura; Goro Kitsukawa; Kanji Oishi
Archive | 1993
Susumu Hatano; Kanji Oishi; Takashi Kikuchi; Yasuhiko Saigou; Hiroshi Fukuta; Kunio Uchiyama; Hirokazu Aoki; Osamu Nishii
Archive | 1985
Yasunori Yamaguchi; Kanji Oishi; Kazuyuki Miyazawa
