Hirokazu Aoki

The Gmicro/500 superscalar microprocessor with branch buffers

The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.<<ETX>>

Design of a second-level cache chip for shared-bus multimicroprocessor systems

The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 mu m CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic. >

A PA-RISC microprocessor PA/50L for low-cost systems

The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities.<<ETX>>