Osamu Nishii

SH4 RISC multimedia microprocessor

Unique, floating-point length-4 vector instructions prove more effective than conventional SIMD architecture for 3D graphics processing.

A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit

This 200 MHz CMOS 2-issue superscalar microprocessor is redesigned with a 0.25 /spl mu/m 5-metal-layers CMOS process (L/sub eff/=0.20 /spl mu/m). In this chip 3.2M transistors are implemented in a 7.6/spl times/7.6 mm/sup 2/ die. This chip for low-cost graphic, embedded applications achieves 1.4 GFLOPS at 200 MHz with low-power consumption. This chip integrates CPU, FPU, 8 kB direct-mapped instruction cache (IC), 16 kB direct-mapped data cache (DC), MMU (64-entry unified TLB and 4-entry ITLB), bus interface logic, and six peripherals which are DMAC, timer unit (TMU), real time clock (RTC), serial comm. interface (SCI), interrupt controller (INTC), and emulation/debug unit (EMU). The bus interface provides glueless connections to SRAM, DRAM, SDRAM, burst-ROM, and PCMCIA, bus operation includes 8-, 16-, 32-, and 64b bus widths.

A 1000 MIPS BiCMOS microprocessor with superscalar architecture

A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.<<ETX>>

On-chip multiple superscalar processors with secondary cache memories

The development of an experimental high-performance microprocessor chip based on a 0.3- mu m BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in parallel. The chip performs 1000 MIPS when instructions and data are fetched from primary caches. It also includes a four-wave interleaved secondary cache assessed in parallel according to a split-bus protocol, to reduce shared memory conflicts. The VLSI architecture and design results of this chip are described.<<ETX>>

Design of a second-level cache chip for shared-bus multimicroprocessor systems

The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 mu m CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic. >

A PA-RISC microprocessor PA/50L for low-cost systems

The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities.<<ETX>>