Kanwal Jit Singh

Demonstration of a reliable high-performance and yielding Air gap interconnect process

Capacitance coupling in copper low-k interconnects can be further reduced by implementing Air gaps in the intra-layer dielectric. This paper describes the evaluation of an integrated Air gap technology using 32 and 22 nm node technology vehicles. Electrical, reliability, and yield results are presented.

Demonstration of an electrically functional 34 nm metal pitch interconnect in ultralow-k ILD using spacer-based pitch quartering

The patterning of a 34 nm metal pitch interconnect was realized using a spacer-based pitch quartering scheme. The pattern is transferred into an ultralow-k ILD using a process that avoids ILD buckling and structure collapse. Resulting features were metallized with copper, and electrically characterized. Measurement results show expected trends with drawn dimensions.

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Nanoscale Buckling of Ultrathin Low-k Dielectric Lines during Hard-Mask Patterning.

Commonly known in macroscale mechanics, buckling phenomena are now also encountered in the nanoscale world as revealed in todays cutting-edge fabrication of microelectronics. The description of nanoscale buckling requires precise dimensional and elastic moduli measurements, as well as a thorough understanding of the relationships between stresses in the system and the ensuing morphologies. Here, we analyze quantitatively the buckling mechanics of organosilicate fins that are capped with hard masks in the process of lithographic formation of deep interconnects. We propose an analytical model that quantitatively describes the morphologies of the buckled fins generated by residual stresses in the hard mask. Using measurements of mechanical properties and geometric characteristics, we have verified the predictions of the analytical model for structures with various degrees of buckling, thus putting forth a framework for guiding the design of future nanoscale interconnect architectures.

Patterning challenges in the fabrication of 12 nm half-pitch dual damascene copper ultra low-k interconnects

Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.

A crossbar network for silicon quantum dot qubits

Quantum dots take a shortcut toward practical quantum information. The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. To increase the number of qubits to the thousands or millions of qubits needed for practical quantum information, we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for nonplanar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates enable qubit addressability and readout. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning-noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future.

Unique Size-Dependent Challenges for BEOL Cleans in the Patterning of Sub-20 nm Features

BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moores law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratios, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Youngs modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .

UV-assisted modification and removal mechanism of a fluorocarbon polymer film on low-k dielectric trench structure.

In this study, we report the first chemical characterization of a plasma-deposited model fluoropolymer on low-k dielectric nanostructure and its decomposition in UV/O2 conditions. Carbonyl incorporation and progressive removal of fluorocarbon fragments from the polymer were observed with increasing UV (≥230 nm) irradiation under atmospheric conditions. A significant material loss was achieved after 300 s of UV treatment and a subsequent wet clean completely removed the initially insoluble fluoropolymer from the patterned nanostructures. A synergistic mechanism of UV light absorption by carbonyl chromophore and oxygen incorporation is proposed to account for the observed photodegradation of the fluoropolymer.

Picosecond ultrasonic study of surface acoustic waves on titanium nitride nanostructures

We have measured surface acoustic waves on nanostructured TiN wires overlaid on multiple thin films on a silicon substrate using the ultrafast pump-probe technique known as picosecond ultrasonics. We find a prominent oscillation in the range of 11–54 GHz for samples with varying pitch ranging from 420 nm down to 168 nm. We find that the observed oscillation increases monotonically in frequency with decrease in pitch, but that the increase is not linear. By comparing our data to two-dimensional mechanical simulations of the nanostructures, we find that the type of surface oscillation to which we are sensitive changes depending on the pitch of the sample. Surface waves on substrates that are loaded by thin films can take multiple forms, including Rayleigh-like waves, Sezawa waves, and radiative (leaky) surface waves. We describe evidence for detection of modes that display characteristics of these three surface wave types.

Characterization of Post Etch Residues on Patterned Porous Low-k Dielectric Using Multiple Internal Reflection Infrared Spectroscopy

The introduction of porous ultralow-k (ULK) dielectrics into Cu metal interconnect continues to pose major BEP integration difficulties beyond 32 nm. As stated in the2009 ITRS Roadmap, “Etching and ashing processes are among the worst processes for inducing damage to low-k materials, affecting not only defectivity, but also electrical reliability”. To decrease the dielectric constant, the porosity of organosilicate glass (OSG) was varied through the replacement of Si-O with Si-C bonds with plasma-enhanced chemical vapor deposition. This carbon-doping process raises the carbon content in OSG and significantly erodes the inherent robustness as compared to inorganic glass dielectrics. On the other hand, the ULK OSG with higher carbon content make it more like an organic photoresist and easily suffers collateral plasma-induced damages during RIE photoresist stripping. In addition, carbon stripping by plasma processes also makes low-k ILDs more prone to water damage during subsequent wet cleans processes. Consequently, the successful patterning of next-generation ULK/Cu interconnects through various non-damaging etching, ashing and cleaning processes represents an increasingly challenging task to the semiconductor industry Besides the challenge of handling weak porous ULK materials, a lack of sensitive metrology to guide systematic development of plasma etching, restoration and cleaning processes is the major stumbling block. Currently, all known characterization techniques in use lack required “specificity or sensitivity” to be useful as a reliable etching process monitoring tool. For example, XPS and TOFSIMS provide only “elemental composition” changes in ULK ILD as well as polymers generated. However, chemical, bonding and structural information are needed to accurately access the ULK ILD integrity, cross linking densities of etch residues and subsequent cleanability. Alternatively, infrared spectroscopy (IR) provides “bonds fraction” data of the ULK ILD and is very useful in revealing plasmainduced ILD damage. However, transmission IR as well as external ATR-IR lacks the “sensitivity” to be useful in monitoring the progression of etching/cleaning processes, especially for deep sidewalls in the patterned wafers. In this presentation, we report the development of a new monitoring metrology that utilizes Multiple Internal Reflection Infrared Spectroscopy (MIR-IR) as a sensitive characterization tool to guide the development of cleans-friendly plasma etches with minimal ULK ILD damages. Previously, we have successfully utilized MIR-IR to characterize chemical bonding of hydrogen termination, trace organic adsorption and plasma deposited polymer thin film on silicon wafer surface with sub-monolayer sensitivity [1-3]. As shown in Figure 1, MIR-IR is capable of monitoring plasma generated polymer thin film of 18 nm with excellent spectra resolution that give useful chemical bonding information. MIR-IR utilizes the silicon wafer (including patterned ULK wafer) itself as an IR waveguide to enable multiple total internal reflections which greatly enhances IR measuring sensitivity. Therefore, MIR-IR possesses a unique capacity of identifying specific functional groups of deposited thin films (sub 10 nm) and monitoring their corresponding reactivity evolution influenced by plasma process. We anticipate new insights obtained on the chemical, structural and bonding modification across ULK ILD interfaces will facilitate development of plasma etching and post etch cleaning techniques that minimize dielectric damage.