Christopher J. Jezewski

Demonstration of an electrically functional 34 nm metal pitch interconnect in ultralow-k ILD using spacer-based pitch quartering

The patterning of a 34 nm metal pitch interconnect was realized using a spacer-based pitch quartering scheme. The pattern is transferred into an ultralow-k ILD using a process that avoids ILD buckling and structure collapse. Resulting features were metallized with copper, and electrically characterized. Measurement results show expected trends with drawn dimensions.

Process technology scaling in an increasingly interconnect dominated world

The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Nanoscale Buckling of Ultrathin Low-k Dielectric Lines during Hard-Mask Patterning.

Commonly known in macroscale mechanics, buckling phenomena are now also encountered in the nanoscale world as revealed in todays cutting-edge fabrication of microelectronics. The description of nanoscale buckling requires precise dimensional and elastic moduli measurements, as well as a thorough understanding of the relationships between stresses in the system and the ensuing morphologies. Here, we analyze quantitatively the buckling mechanics of organosilicate fins that are capped with hard masks in the process of lithographic formation of deep interconnects. We propose an analytical model that quantitatively describes the morphologies of the buckled fins generated by residual stresses in the hard mask. Using measurements of mechanical properties and geometric characteristics, we have verified the predictions of the analytical model for structures with various degrees of buckling, thus putting forth a framework for guiding the design of future nanoscale interconnect architectures.

Patterning challenges in the fabrication of 12 nm half-pitch dual damascene copper ultra low-k interconnects

Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.

Resistance and electromigration performance of 6 nm wires

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.

Cu film thermal stability on plasma cleaned polycrystalline Ru

The first part of this study examined oxide stability and cleaning of Ru surfaces. The surface reactions during H2 plasma exposure of Ru polycrystalline films were studied using x-ray photoelectron spectroscopy (XPS). The ∼2 monolayer native Ru oxide was reduced after H-plasma processing. However, absorbed oxygen, presumably in the grain boundaries, remains after processing. A vacuum thermal anneal at 150 °C substantially removes both surface oxide and absorbed oxygen which is attributed to a reduction by carbon contamination. The second part of the study examined the thermal stability of Cu on a Ru layer. The thermal stability or islanding of the Cu film on the Ru substrate was characterized by in situ XPS. After plasma cleaning of the Ru adhesion layer, the deposited Cu exhibited full coverage. In contrast, for Cu deposition on the Ru native oxide substrate, Cu islanding was detected and was described in terms of grain boundary grooving and surface and interface energies. The oxygen in the grain boundar...

Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.