Hui Jae Yoo

Demonstration of a reliable high-performance and yielding Air gap interconnect process

Capacitance coupling in copper low-k interconnects can be further reduced by implementing Air gaps in the intra-layer dielectric. This paper describes the evaluation of an integrated Air gap technology using 32 and 22 nm node technology vehicles. Electrical, reliability, and yield results are presented.

Demonstration of an electrically functional 34 nm metal pitch interconnect in ultralow-k ILD using spacer-based pitch quartering

The patterning of a 34 nm metal pitch interconnect was realized using a spacer-based pitch quartering scheme. The pattern is transferred into an ultralow-k ILD using a process that avoids ILD buckling and structure collapse. Resulting features were metallized with copper, and electrically characterized. Measurement results show expected trends with drawn dimensions.

Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process

A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.

Patterning challenges in the fabrication of 12 nm half-pitch dual damascene copper ultra low-k interconnects

Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.

Resistance and electromigration performance of 6 nm wires

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.

Nanoscale tomographic reconstruction of the subsurface mechanical properties of low-k high-aspect ratio patterns

In this work, intermittent contact resonance atomic force microscopy (ICR-AFM) was performed on high-aspect ratio a-SiOC:H patterned fins (100 nm in height and width from 20 to 90 nm) to map the depth and width dependencies of the material stiffness. The spatial resolution and depth sensitivity of the measurements were assessed from tomographic cross-sections over various regions of interest within the 3D space of the measurements. Furthermore, the depth-dependence of the measured contact stiffness over the scanned area was used to determine the sub-surface variation of the elastic modulus at each point in the scan. This was achieved by iteratively adjusting the local elastic profile until the depth dependence of the resulted contact stiffness matched the depth dependence of the contact stiffness measured by ICR-AFM at that location. The results of this analysis were assembled into nanoscale sub-surface tomographic images of the elastic modulus of the investigated SiOC:H patterns. A new 3D structure-property representation emerged from these tomographic images with direct evidence for the alterations sustained by the structures during processing.

Simple test vehicle for metal fill and resistance of sub-8nm nanowire

Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.

Demonstration of a sidewall capacitor to evaluate dielectrics and metal barrier thin films

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Demonstration of new planar capacitor (PCAP) vehicles to evaluate dielectrics and metal barrier thin films

Planar capacitors can quickly test material properties of metals and dielectrics for interconnects. A sidewall capacitor device is used to evaluate metal thin-film barriers. Etch stop planar capacitors in turn can test multi-layer etch stops, exposing differences between leaky and good etch stop films. Fillable planar capacitors are also fabricated and results presented for that class of fill materials.

Nickel silicide for interconnects

Nickel silicide is an attractive option for interconnects at small dimensions because of its short electron mean free path and good electromigration behavior. Nickel silicide interconnects can be integrated using either a subtractive or damascene process. Precise control of final metal composition ratio is important for obtaining low resistivity, as shown in thin-film and patterned structure measurements.