Karen A. Nummy

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Monitoring process-induced focus errors using high-resolution flatness metrology

Reducing focus errors during optical lithography patterning is crucial for minimizing defects and for achieving the desired critical dimension uniformity (CDU). Factors that contribute to lithography defocus originate from both within and outside the exposure tools. Wafer geometry and topography have been shown to be a major contributor to the focus budget, but decoupling wafer issues from scanner tooling / chuck signatures is far from trivial. In this paper we will review how the use of flatness metrology in a 22nm manufacturing environment improved our ability to measure focus errors as well as enabled the decoupling of error between tooling and wafer sources. We will also review several examples of experimental datasets demonstrating how this wafer shape measurement technique has provided unique insight to the nature of topography based focus error, as well as provide a valuable learning mechanism for driving improvement in process cycles of learning.

Modeling and Extraction of Effective Lateral Doping Profile Using the Relation of On-Resistance vs. Overlap Capacitance in (100) and (110)-Oriented MOSFETs

A comprehensive technique for the accurate extraction of the effective lateral doping abruptness and the spreading resistance components is applied to both Si (100) and Si (110) MOSFETs. The spreading resistance components under extension-to-gate overlap and spacer regions are successfully correlated to the lateral extension (EXT) doping abruptness by the relationship between on-resistance (Ron) and overlap capacitance response (Cov). The lateral doping profile difference is extracted between (100) and (110) PMOS, which successfully explains higher external resistance in measured (110) PMOS.