G. Badenes

Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability

The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuits frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuits logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible.

Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 /spl mu/m CMOS technology

An electrostatic discharge (ESD) evaluation of a silicided 0.25 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technology is carried out by HEM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Silicide and Shallow Trench Isolation line width dependent stress induced junction leakage

For the first time, the influence of the mechanical stress, induced by silicidation of active areas in combination with stress from the Shallow Trench Isolation (STI), on the leakage current of n+/p and p+/n junctions has been studied. When scaling down the width of the diode structure from 2 /spl mu/m to 0.25 /spl mu/m, the anisotropic compressive stress in the junction area increases drastically. These experiments prove that regardless the contributions of the area and the perimeter to the total leakage current of this type of diode structure (=20%), 80% of the total leakage current of this diode structure can be attributed to stress and that this part of the leakage current increases with almost a factor of two when reducing the junction width from 2 /spl mu/m to 0.25 /spl mu/m. Therefore, in order to keep the diode leakage variation as low as possible when further down scaling the junction and the trench dimensions, the formation of a low stress silicide in combination with a low stress isolation technology is essential.

Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity

The continuous downscaling of CMOS devices aims at cost reduction and performance improvement. Process development constantly faces new constraints and integrates breakthroughs to overcome them. In deep submicron CMOS generations, scalability is in part limited by conflicting needs for shallow silicided junctions and low junction leakage. Both requirements can be met using elevated source/drain (/sup E/S/D) architecture. Although this solution has long been established, its avoidable extra complexity has delayed its introduction in industrial mainstream technologies. However, as device scaling continues, process windows are reducing critically. As a result, /sup E/S/D architecture is attracting a growing interest. This paper reports on a 0.18 /spl mu/m CMOS technology featuring /sup E/S/D made with sacrificial selective epitaxy. This technology is examined from the standpoints of manufacturability and performance improvement. In contrast to most /sup E/S/D approaches, the selective epitaxy is done after junction formation, resulting in increased process window. Our /sup E/S/D process leads to dc and rf device performance enhancements. Nevertheless, the same functionality gains were achieved by a fine-tuning of the reference conventional low-cost process. Process window reduction will require /sup E/S/D for generations below 0.13 /spl mu/m.

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

Abstract The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF2 is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.

A New Dummy‐Free Shallow Trench Isolation Concept for Mixed‐Signal Applications

Shallow trench isolation (STI) is becoming the mainstream lateral isolation module for deep submicrometer technologies. It is generally accepted that dummy active areas need to he implemented due to the limited within-chip uniformity associated with the chemical mechanical polishing step. Dummy active areas, however, are problematic when used in mixed-signal technologies due to the increased capacitive coupling and noise associated with them. To solve this problem, we developed an STI module that ensures minimum oxide dishing and nitride erosion without the need for dummy active areas. This paper presents and discusses the fabrication process for this STI module and the results obtained with it. We have successfully implemented the new dummy-free STI process in a 0. 18 μm technology.

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5 nm and supply voltage of 1.5 V. The optimal performance is achieved by minimizing parasitic effects. The influence of experimental splits in source/drain (S/D) extension dose, S/D HDD dose and spike RTA on the reduction of series resistance and poly-depletion effect is studied. The role of the HALO implantation in optimization is investigated in detail.

Investigation of stress in shallow trench isolation using UV micro-Raman spectroscopy

Abstract We present an investigation of local mechanical stress in shallow trench isolation by UV micro-Raman spectroscopy. UV light (364 nm) penetrates only 15 nm into silicon. In contrast to conventional micro-Raman spectroscopy using visible light only the stress very close to the surface is monitored. In this way, local areas of high stress can be detected, that are not seen with longer wavelength light due to averaging. We demonstrate the advantages of the UV method by an investigation of the influence of different trench oxide densification ambients on the amount of mechanical stress in the silicon substrate. We find, that large mechanical stress up to 800 MPa is introduced at the active area edges during densification in steam ambient. This stress is caused by the formation and growth of a bird’s beak, which may lead to defect creation especially in small trenches. This investigation demonstrates the capability to use UV micro-Raman spectroscopy in ULSI technology.

Investigation by Convergent Beam Electron Diffraction of the Stress around Shallow Trench Isolation Structures

Convergent beam electron diffraction (CBED) is used in this study to investigate the stress distribution around shallow trench isolation (STI) structures. Attention is given to the influence of the different processing parameters and the width and spacing of the structures. The use of a wet or a dry pregate oxidation is found to have a strong influence on the stress behavior. Isolated lines show more stress, leading to the formation of defects in the silicon substrate if a wet pregate oxidation is used. The CBED analyses are compared with micro-Raman and bright-field transmission electron microscopy measurements.

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

It has been known that using selective epitaxial growth (SEG) of silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture also reduces the gate resistance by enabling a T-shape gate and allowing thicker silicides, which is beneficial for RF-CMOS regarding increased maximum oscillation frequency (f/sub max/) and lowering of the noise figure (NF). In this paper, we report the impact of the SEG-deep source/drain implant (DSDI) process sequence and Co silicide thickness on DC and RF performance of NMOS transistors. Up to a 28%-45% improvement in f/sub max/ is achievable due to a T-shaped gate and thicker Co, made possible by an elevated source/drain (/sup E/S/D) architecture. The maximum transconductance (g/sub m/) of the /sup E/S/D device reaches a value of 1100 mS/mm, which in turn gives a very high f/sub T/ of 150 GHz. The low gate sheet resistance obtained with this architecture is also very beneficial for suppressing noise figure in the low-noise amplifier (LNA) circuit demonstrated in this paper. Furthermore, it is shown by simulation that the noise performance of an RF LNA improves due to the SEG and the Co thickness in the T-shaped gate of the NMOS transistor.