Kathy Boucart

Double-Gate Tunnel FET With High-

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.

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In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin silicon film as a key technology booster for the performance of all-silicon tunnel FETs. We demonstrate by simulation that a Gaussian tensile-strain profile with a maximum placed at the source side of a nanowire tunnel FET with a 50-nm channel length provides an optimized solution for a low-standby-power switch. This leads to the following: (1) ultralow I off (more than three decades lower than in the case of a device on uniformly strained silicon); (2) boosting of I on (more than one decade higher compared to a silicon reference); and (3) an average subthreshold swing S avg of 48 mV/dec at room temperature. Furthermore, the inherent finite drain threshold voltage of the tunnel FET, which could be a disadvantage for logic design with tunnel FETs, is exponentially reduced with the strain-induced bandgap shrinkage at the source side.

Gate Dielectric

In this paper we propose a novel design for a double gate tunnel field effect transistor (DG TFET), for which the simulations show significant improvements compared with single gate devices with a SiO 2 gate dielectric. For the first time, double gate devices using a high-K gate dielectric are explored, showing on-current as high as 1 mA for a gate voltage of 1.2 V, reduced off-current as low as 0.1 fA, improved average subthreshold swing of 52 mV/decade, and a minimum point slope of 18 mV/decade. An Ion/Ioff ratio of more than 1012 is shown

Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

In this paper we study the sensitivity to parameter fluctuations for an optimized double-gate silicon Tunnel FET with a high-k gate dielectric. The impacts of the variability of the dielectric thickness, doping profile at the tunnel junction, silicon body thickness, alignment of the gate dielectric to the tunnel junction, device length, and band gap at the tunnel junction, on the device performance are systematically studied. One parameter is varied at a time to show the resulting fluctuations of the device characteristics. Gate dielectric thickness and doping junction width are pinpointed as the parameters requiring the tightest control during Tunnel FET fabrication in order to limit characteristic fluctuations. Body thickness and gate dielectric alignment with the tunnel junction may also need tight control depending on whether the target values are within a range where the characteristics are highly sensitive.

Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric

This work reports on the physical definition and extraction of threshold voltage in tunnel FETs based on numerical simulation data. It is shown that the tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, V_TG, and one in terms of drain voltage, V_TD. These threshold voltages can be physically defined based on the saturation of the barrier width narrowing with respect to V_G or V_D. The extractions of V_TG and V_TD are performed based on the transconductance change method in the double gate tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these threshold voltages, current, conductance characteristics, g_m/I_D and g_m/g_ds of the tunnel FET is investigated for the first time.

A simulation-based study of sensitivity to parameter fluctuations of silicon Tunnel FETs

16MHz and 91MHz micromechanical resonators based on the Resonant Suspended-gate MOSFET (RSG-MOSFET) architecture are demonstrated. A fabrication process using a polysilicon sacrificial layer and an aluminum-silicon alloy (AlSi 1%) suspended-gate was developed. Static and dynamic electrical characteristics of the Clamped-Clamped beam (CC-beam) resonator have been investigated in order to explain the device behavior. The lowest reported actuation voltage for a MEMS resonator, less than 1V, makes the resonator compatible with standard CMOS voltages. The actuation voltage dependence on the MOSFET characteristics and the threshold voltage is explained. A resonant frequency tuning of 750kHz was achieved by a 240mV DC voltage variation, and a quality factor of Q= 641 was calculated from measurements in vacuum.

Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design

We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells. We report Ion/Ioff larger than 105 and Ioff on the order of 100 fA/μm in micrometer-scale p-type Fe-TFETs fabricated on ultrathin-film (fully depleted) silicon-on-insulator substrates with a SiO2/Al2O3/ PVDF gate stack processed at low temperature. The hysteretic characteristics of the TFETs with Fe gate stacks are revealed by static experiments, and the principle of the proposed device is further confirmed by 2-D calibrated numerical simulations. Low temperature measurements down to 77 K confirm the reduced sensitivity of the TFET subthreshold swing to temperature and distinguish them from fabricated reference Fe metal-oxide-semiconductor FETs. Finally, we investigate the potential of Fe-TFETs as 1T memory devices and find retention times on the order of a few minutes at room temperature.

Ultra-Low Voltage MEMS Resonator Based on RSG-MOSFET

This paper discusses three categories of small slope electronic switches: the tunnel FET, the IMOS and the NEM-FET, which are expected to bring added value compared to CMOS by presenting an abrupt subthreshold slope, smaller than the physical limit, 60mV/decade, of the solid-state MOS transistor at room temperature. Recent results and future promises are reported.

The Hysteretic Ferroelectric Tunnel FET

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile with a maximum of strain higher than 3GPa at the BTB source junction could act as an effective performance Tunnel FET enabling the cancelation of the drain threshold voltage. We study and report in detail the contributions of main technology boosters of all-silicon Tunnel FETs: (i) strained source, (ii) high-k gate dielectric, (iii) multiple-gate, (iv) oxide alignment to i-region and (v) channel length scaling, as an additive device optimization enabling future sub-1V operation.