Kirsten E. Moselund

Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200 MPa to 2 GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

Cointegration of Gate-All-Around MOSFETs and Local Silicon-on-Insulator Optical Waveguides on Bulk Silicon

In this work we present a bulk silicon technology platform able to cointegrate gate-all-around (GAA) MOSFETs and local SOI waveguides with pentagonal cross section. Wire diagonals of 100-800 nm are obtained using a lithographic resolution of 0.8 mum. Well-functioning triangular multigate MOSFETs are reported, and tested up to 150 degC. A significant increase is observed in the low-field mobility mu0 for small devices (Weffles500 nm), which is attributed to local volume inversion in the corners. Preliminary characterization of the optical waveguides is carried out, showing optical losses of a few dB/cm. The processing is entirely CMOS compatible, does not require access to advanced lithography equipment, and is based on a silicon bulk substrate. Thus, this technology might serve as the basis for a low-cost, high-performance optical signaling platform

Local volume inversion and corner effects in triangular gate-all-around MOSFETs

We report on the fabrication and measurement of triangular gate-all-around (GAA) and tri-gate devices. On the small triangular cross-section devices we observe a significant enhancement of the extracted carrier mobility (up to ~1000cm2/Vs). We assign this effect to enhanced conduction in the sharp corners of our device, and local volume inversion. The new concept of local volume inversion is supported by a boosting of experimental gm in the subthreshold region. Furthermore, we have carried out 3D numerical simulations, which support these findings

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the decoder circuit for NW crossbar arrays, based on the existing technological solutions for threshold voltage differentiation of NW devices. This is equivalent to using a multivalued logic addressing scheme. With this approach, it is possible to reduce the decoder size and keep it defect tolerant. We formally define two types of multivalued codes (i.e., hot and reflexive codes), and we estimate their yield under high variability conditions. Multivalued hot decoders yield better area saving than n-ary reflexive codes, and under severe conditions, reflexive codes enable a nonvanishing part of the code space to randomly recover. The choice of the optimal combination of decoder type and logic level saves area up to 24%. We also show that the precision of the addressing voltages when a high variability affects the threshold voltages is a crucial parameter for the decoder design and permits large savings in memory area. Moreover, a precise knowledge about the variability level improves the design of memory decoders by giving the right optimal code.

Small Slope Micro/Nano-Electronic Switches

This paper discusses three categories of small slope electronic switches: the tunnel FET, the IMOS and the NEM-FET, which are expected to bring added value compared to CMOS by presenting an abrupt subthreshold slope, smaller than the physical limit, 60mV/decade, of the solid-state MOS transistor at room temperature. Recent results and future promises are reported.

Abrupt current switching due to impact ionization effects in Ω-MOSFET on low doped bulk silicon

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8times1014 cm-3) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of ID(VDS) are observed at high drain voltage (VDS>11 V) on transistors that have short channel effects (L=0.9-10 um). This is explained by the accumulation of a hole pocket under the gate due to the formation of a saddle point region. An outstanding feature is that this effect can be exploited to abruptly switch from low to high current (2 decades of current) states of ID(VGS) characteristics with ultra-abrupt slopes of 5 to 10 mV/dec. Moreover, the hysteresis window DeltaVGS~500 mV is suitable for DRAM memory. Dynamic switching characteristics and a retention time of up to tens of seconds are originally demonstrated. The proposed Omega-MOSFET stands as a very promising alternative to I-MOS devices, being more scalable and integrable on a standard (low cost) bulk-Si Multi-Gate FET platform. Its experimental performances are promising for both small-slope switches and dynamic RAM memories.

Hysteretic inverter-on-a-body-tied-wire based on less-than-10mV/decade abrupt punch-through impact ionization MOS (PIMOS) switch

This work reports for the first time on a cascadable NMOS inverter based on punch-through impact ionization MOSFET (PIMOS) integrated on a single body-tied silicon wire. The PIMOS device acts as a single-transistor-latch and shows abrupt current switching (3-10 mV/dec.) as well as hysteresis in both ID(VDS) and ID(VGS). An inverter gain as high as -80 and a 300 mV hysteresis width in the transfer characteristics are reported at room temperature. Temperature stability of the devices up to 125degC and operation for more than 104 cycles without significant degradation are demonstrated, much beyond the performances of previously reported I-MOS device.

Low temperature single electron characteristics in gate-all-around MOSFETs

This work reports on the fabrication, characterization and modeling of single electron transistor behavior in gate-all-around silicon nanoscale MOS devices. Polysilicon-gated nanowire transistors with triangular cross-sections, ranging from 20 to 250nm are fabricated by an original isotropic etching technique resulting in localized-SOI on bulk-Si wafers. Low temperature (T<20K) characteristics show Coulomb blockade in ID-VD and periodic oscillations in I D-VG. Two modeling approaches are discussed and critically compared to explain the experimental results: (i) orthodox theory of single electron transistor; and (ii) one-dimensional sub-bands formation

Materials and Devices for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

In this chapter, we review some of the most recent results in these areas and put them in a unified context that covers a very wide range, from materials to system design. The first section presents a top-down silicon nanowire fabrication platform for high-mobility gate-all-around (GAA) MOSFETs and impact-ionization devices. Ferroelectric FET with sub-100-nm copolymer P(VDF-TrFE) gate dielectric are examined in the next section for nonvolatile memory applications, which is a very promising direction toward future high-density memory arrays, followed by a discussion of materials for piezoelectric nanodevices in the last section.

Scaling SOI photonics to micron and sub-micron devices

Scaling photonics devices in silicon on insulator (SOI) substrates has the potential to address important issues in the fields of optical telecommunications and optical interconnects. Silicon, is highly transparent in the infra-red spectral region and etching ribs or rectangular channels can create the condition for single-mode low-loss waveguiding. The high index difference between silicon and the surrounding media, typically SiO2 or air, is extremely favorable for the development of ultra-compact photonic devices. Active functionality can be performed by free charge injection in the waveguide resulting in a phase shift of the propagating fundamental mode. Moreover this technology is fully CMOS compatible allowing a low-cost monolithic integration of control electronics. Limitations deriving from an aggressive scaling of SOI waveguides are a lowered efficiency in the in-out coupling of light and higher propagation losses due to increased roughness scattering. We report on the perspectives and issues of scaling SOI photonics devices for both passive and active functionality. Results show that scaled waveguides can have very low bending radii down to the micrometer range. We also propose a new method and architecture for light phase modulation based on a Schottky barrier diode; a process flow will be analyzed and validated experimentally.