Katrin Sidler

Metallic Nanowires by Full Wafer Stencil Lithography

Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale.

Analysis of the blurring in stencil lithography.

A quantitative analysis of blurring and its dependence on the stencil-substrate gap and the deposition parameters in stencil lithography, a high resolution shadow mask technique, is presented. The blurring is manifested in two ways: first, the structure directly deposited on the substrate is larger than the stencil aperture due to geometrical factors, and second, a halo of material is formed surrounding the deposited structure, presumably due to surface diffusion. The blurring is studied as a function of the gap using dedicated stencils that allow a controlled variation of the gap. Our results show a linear relationship between the gap and the blurring of the directly deposited structure. In our configuration, with a material source of approximately 5 mm and a source-substrate distance of 1 m, we find that a gap size of approximately 10 microm enlarges the directly deposited structures by approximately 50 nm. The measured halo varies from 0.2 to 3 microm in width depending on the gap, the stencil aperture size and other deposition parameters. We also show that the blurring can be reduced by decreasing the nominal deposition thickness, the deposition rate and the substrate temperature.

Stenciled conducting bismuth nanowiresa)

Stencil lithography is used here for the fabrication of bismuth nanowires using thermal evaporation. This technique provides good electrical contact resistance by having the nanowire structure and the contact pads deposited at the same time. It has also the advantage of modulating nanowires’ height as a function of their width. As the evaporated material deposits on the stencil mask, the apertures shrink in size until they are fully clogged and no more material can pass through. Thus, the authors obtain variable-height (from 27 to 95 nm) nanowires in the same evaporation. Upon their morphological (scanning electron microscopy and atomic force microscopy) and electrical characterizations, the authors obtain their resistivity, which is independent of the nanowire size and is the lowest reported for physical vapor deposition of Bi nanowires (1.2×10−3 Ω cm), only an order of magnitude higher than that of bulk bismuth.

Resistless Fabrication of Nanoimprint Lithography (NIL) Stamps Using Nano-Stencil Lithography

In order to keep up with the advances in nano-fabrication, alternative, cost-efficient lithography techniques need to be implemented. Two of the most promising are nanoimprint lithography (NIL) and stencil lithography. We explore here the possibility of fabricating the stamp using stencil lithography, which has the potential for a cost reduction in some fabrication facilities. We show that the stamps reproduce the membrane aperture patterns within ±10 nm and we validate such stamps by using them to fabricate metallic nanowires down to 100 nm in size.

All-stencil transistor fabrication on 3D silicon substrates

The standard lithographic techniques to fabricate electronic components involve the use of polymers, baking steps and chemicals. This typically restricts their application to flat substrates made up of standard materials. Stencil lithography has been proposed as a stable alternative to the standard lithographic techniques. In this paper, we demonstrate the completely resistless all-through-stencil fabrication of electronic components, by performing all essential fabrication steps—implantation, etching and metallization—using stencil lithography. This is performed on a planar substrate as well as on pre-patterned 3D substrates, thus showing the potential of this technique for applications in the field of accelerometers, pressure, gas and radiation sensors.

Double-gate pentacene TFTs with improved control in subthreshold region

In this work a double-gate pentacene TFT architecture is presented. The devices are fabricated on a polyimide substrate using three aligned levels of stencil lithography along with standard photolithography, which enable a soft yet well-controlled device processing. The positive impact of the top gate voltage control on reducing the leakage current and significantly improving the subthreshold swing of the device is demonstrated. Moreover, this original design shows good promise for the enhancement of ION/IOFF TFT characteristics.

Minimized blurring in stencil lithography using a compliant membrane

This work reports on advanced stencil lithography using compliant membranes. Compliant membranes are mechanically decoupled from a rigid silicon frame by means of four non planar cantilevers. Compliant membranes are protruding parts which adapt to the surface independently in order to reduce the gap between a membrane and its substrate. FEM simulations show that compliant membranes can vertically deflect 40 μm which is a typical maximal gap. Microapertures were defined using UV lithography and nanoapertures, down to 200 nm in diameter, using FIB. A 100 nm thick aluminum layer was evaporated through compliant and non compliant membranes on a silicon wafer. Subsequent SEM characterizations have shown a smaller halo diameter around the structures patterned by compliant membranes.