Masayoshi Kinoshita

An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique

An on-chip DC/DC converter with high efficiency and low-noise and easy implementation in LSIs is needed for single-supply voltage and low-power operation of LSIs. To obtain high-efficiency, fixed pulse-width modulation (PWM) and zero volt switching (ZVS) adaptive control are used. Operation with efficiency >90% is reported. However, these reports do not discuss low- noise switching operation and easy implementation. These are the most important points for practical use. The specifications for the DC/DC converter are: (1) easy implementation into LSIs as an on-chip DC/DC converter; (2) efficiency over 90% (at Io=80 mA, 3.0 V->2.0 V); (3) output noise below 30 mVp-p. A DC/DC converter which has both efficiency over 92% and 15 mV output noise is incorporated into an LSI.

Mixed body-bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.

Mixed body-bias techniques with fixed Vt and Ids generation circuits

In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, 85% reduction of the delay variation, and 75% improvement of power consumption of SRAM on a mobile processor.

High efficiency and latch-up free switched capacitor up converter on FD-SOI technology

We have developed a latch-up free Switched Capacitor (SC) type voltage up converter on 0.35 /spl mu/m FD-SOI technology. In this paper, we propose approximate theoretic expressions of the power efficiency and the output voltage. A test chip confirms the validity of these theoretic expressions. As a result, we can optimize the performances for various load currents of the up converter. The up converter achieved a power conversion efficiency of 93.5% including self-power. consumption at 1 mA DC load current, where switching frequency is 100 kHz, input voltage is 0.8 V, V out is 1.55 V, and capacitance is 10 /spl mu/F.