Katsumi Shinomura

Horizontal Current Bipolar Transistor With a Single Polysilicon Region for Improved High-Frequency Performance of BiCMOS ICs

A new horizontal current bipolar transistor (HCBT) with a single polysilicon region and a CMOS gate polysilicon near the n⁺ emitter region is integrated with CMOS technology with the addition of two or three masks (three or four masking steps) and a small number of additional fabrication steps. The single-poly HCBT with an optimized collector exhibits f_T and f_max of 51 and 61 GHz, respectively, and an f_TBV_CEO product of 173 GHz · V, which are the best reported HCBT characteristics to date and among the highest performance Si BJTs. An HCBT with only two additional masks to CMOS has f_T and f_max of 43 and 53 GHz, respectively, and an f_TSV_CEO product of 120 GHz · V. The developed innovative fabrication techniques enable a very low-cost BiCMOS platform for wireless communication circuits.

Collector region design and optimization in Horizontal Current Bipolar Transistor (HCBT)

Three different types of the n-collector region of Horizontal Current Bipolar Transistor (HCBT) are analyzed and compared. The optimum n-collector profile suppresses the charge sharing effect between the intrinsic and extrinsic base regions, resulting in the uniform base width and electric field in the intrinsic transistor. This implies a maximum BVCEO and an optimum fTBVCEO product among compared structures. The HCBT with a selectively implanted collector (SIC) is introduced and examined. It reduces RC and increases fT comparing to the other n-collector designs. The analyses give the guidelines for the optimum HCBT design for targeted applications.

Horizontal Current Bipolar Transistor (HCBT) for the low-cost BiCMOS technology

A new Horizontal Current Bipolar Transistor (HCBT) is developed and integrated with a commercial 0.18 µm CMOS technology resulting in a very low-cost BiCMOS technology suitable for wireless applications. The number of fabrication steps is significantly reduced in comparison to conventional vertical-current bipolar transistors. The optimum HCBT performance can be achieved by 3 additional masks to CMOS process while an even simpler version with 2 additional masks is also demonstrated. The integration of HCBT with bulk CMOS is achieved by introducing innovative process steps such as protecting the active transistor region during polysilicon etching by low-resistance native oxide, placement of high-doped emitter and collector regions in oxide trenches etc. The compact HCBT structure has small junction capacitances and fT and fmax of 34 GHz and 45 GHz, respectively, with BVCEO=3.4 V.

Double-Emitter HCBT Structure—A High-Voltage Bipolar Transistor for BiCMOS Integration

Fabrication of a novel high-voltage double-emitter horizontal current bipolar transistor (HCBT) structure integrated with the standard 0.18-μm CMOS and high-speed HCBT is presented. The device takes advantage of 3-D collector charge sharing to achieve full depletion of the intrinsic collector region and to limit the electric field at the base-collector junction. Transistors with BVCEO = 12.6 V, fT ·BVCEO = 160 GHz·V , and β·VA = 28 700 V are demonstrated. The device is fabricated in HCBT BiCMOS process flow without the use of additional lithography masks and represents a zero-cost solution for integration of a high-voltage bipolar device.

Optimization of Horizontal Current Bipolar Transistor (HCBT) technology parameters for linearity in RF mixer

Double-balanced active mixer based on a Gilbert cell is designed and fabricated as the first RF circuit in Horizontal Current Bipolar Transistor (HCBT) technology. The maximum IIP3 of 17.7 dBm at mixer current of 9.2 mA and conversion gain of -5 dB are achieved. Three different HCBT structures are used in a mixer design to examine the effect of process parameters on mixer linearity. The main effect on the linearity has the n-collector doping profile since it governs the onset of Kirk effect. The improvement of 6 dB in IIP3 can be achieved by using the optimum HCBT structure, if switching quad transistors operate at or near the high current region. The circuit model parameters of three HCBT structures are extracted, accurately reproducing the measured device and circuit data.

Examination of novel high-voltage double-emitter horizontal current bipolar transistor (HCBT)

Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing is used to achieve intrinsic base shielding and to limit the electric field across the intrinsic base-collector junction. This is accomplished by the transistor layout i.e. the mask design. Transistors with BVCEO =12.6 V, VA=301 V and fT=12.7 GHz are fabricated in a standard HCBT BiCMOS process flow without the use of the additional lithography masks. Physical behavior of the transistor is thoroughly examined by 3D device simulations.

Examination of Horizontal Current Bipolar Transistor (HCBT) Reliability Characteristics

The reliability characteristics of HCBT are examined for the first time by employing reverse emitter-base (EB) and mixed-mode stresses. Three HCBT structures with different n-collector doping profiles and different oxide etching parameters before polysilicon deposition are measured, exhibiting different behavior at each stress test. Due to the specific HCBT structure, the traps generation causing IB degradation, occurs at different regions, i.e. at EB pn-junction near both the top and the bottom EB oxide for reverse EB stress and only at the bottom EB oxide for mixed-mode stress, as discovered by TCAD simulations. Pre-deposition oxide etching conditions turned out to be critical for IB degradation after reverse EB stress, whereas the n-collector vertical doping profile mostly impacts the trap generation after the mixed-mode stress. The 1/f noise characteristics also show the highest degradation for HCBT structures with the highest stress damage.

Examination of Horizontal Current Bipolar Transistor (HCBT) with double and single polysilicon region

Horizontal Current Bipolar Transistor (HCBT) with implanted n⁺ collector (single-poly HCBT) has a higher f_T and f_max by 50 % and 36%, respectively, comparing to HCBT with polysilicon n⁺ collector (double-poly HCBT). The physical mechanisms responsible for the improvement of f_T and f_max of single-poly HCBT are examined by the measurements of transistors, test structures and by simulations. Besides the current crowding effect, it is shown that R_C dominantly limits f_T in double-poly HCBT. The dominant component of R_C is identified to be the resistance of the interface oxide between the n⁺ polysilicon and the n-hill collector regions.

Design considerations for integration of horizontal current bipolar transistor (HCBT) with 0.18 μm bulk CMOS technology

Horizontal Current Bipolar Transistor (HCBT) is the only bulk-silicon lateral bipolar transistor with state-of-the-art electrical performance published so far [1]. Integration of the HCBT with a commercial 0.18 μm CMOS process has been demonstrated [2] and yields a very low-cost BiCMOS technology platform suitable for wireless applications.

RF bipolar transistors in CMOS compatible technologies

A RF bipolar transistor integrated into a standard 0.35 /spl mu/m CMOS process is presented. This BiCMOS technology features a single-poly NPN transistor with simulated f/sub /spl tau//=16 GHz and BV/sub CEO/=6.4 V. With implanted base and no trench isolation, this device is truly compatible with standard CMOS technology and offers good performance compared to previously published results of BiCMOS technologies.