Katsushi Nagaba

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symposium on vlsi circuits | 2007

Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; Hideyuki Tabata; Atsushi Inoue; Toshiyuki Takahashi; Toshifumi Shano; Yukio Komatsu; Katsushi Nagaba; Mitsuhiko Kosakai; Noriaki Motohashi; Kazuhisa Kanazawa; Kenichi Imamiya; Hiroto Nakai

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.

IEEE Journal of Solid-state Circuits | 2008

Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; Hideyuki Tabata; Atsushi Inoue; Toshiyuki Takahashi; Toshifumi Shano; Yukio Komatsu; Katsushi Nagaba; Mitsuhiko Kosakai; Noriaki Motohashi; Kazuhisa Kanazawa; Kenichi Imamiya; Hiroto Nakai; Menahem Lasser; Mark Murin; Avraham Meir; Arik Eyal; Mark Shlick

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.

Archive | 1997