Katsuyoshi Kodera

Novel error mode analysis method for graphoepitaxial directed self-assembly lithography based on the dissipative particle dynamics method

Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full advantage of DSAL requires diminishing not only systematic error modes but also random error modes by carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only systematic errors but also random errors qualitatively by simulations.

Dissipative particle dynamics simulations to optimize contact hole shrink process using graphoepitaxial directed self-assembly

Dissipative particle dynamics (DPD) simulations are utilized to optimize contact hole shrink process using graphoepitaxial directed self-assembly (DSA). In this work, poly (styrene-block-methyl methacrylate) (PS-b-PMMA) was employed. In the contact hole shrink process, PS residual layer was formed on the bottom floor of the hole type prepattern. To realize reliable contact hole shrink process, minimization of the thickness of PS residual layer was one of the key issues. It was found that the minimization of the thickness of the PS residual layer and optimization of threedimensional configuration of the PMMA domain was trade-off relationship. By using DPD simulations, the parameters were successfully optimized to achieve residual layer free contact hole shrink of DSA lithography.

Directed self-assembly lithography using coordinated line epitaxy (COOL) process

In this study, half-pitch (HP) 15 nm line-and-space (L/S) metal wires were successfully fabricated and fully integrated on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA, we developed a simple sub-15 nm L/S patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP), which utilizes trimming resist and shallow etching spin-on-glass (SOG) as pinning guide[1]-[4]. From the results of defect inspection after SOG etch using Electron Beam (EB) inspection system, defects were classified as typical DSA defects or defects relating to DSA pattern transfer. From the evaluation of DSA L/S pattern Critical Dimension (CD), roughness and local placement error using CD-SEM, it is considered that isolated PS lines are placed at the centerline between guides and that placement of paired PS lines depends on the guide width. The control of the guide resist CD is the key to local placement error and the paired lines adjacent to the guide shifted toward the outside (0.5 nm) along the centerline of the isolated line after SOG etch. We demonstrated fabrication of HP 15 nm metal wires in trenches formed by the DSA process with reactive ion etching (RIE), followed by metal chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). By SEM observation of alignment errors between the trenches and connect spaces, overlay shift patterns (-4 nm) in guide lithography mask were fabricated without intra-wafer alignment errors.

Defect-aware process margin for chemo-epitaxial directed self-assembly lithography using simulation method based on self-consistent field theory

We proposed a new concept of “defect-aware process margin.” Defect-aware process margin was evaluated by investigating the energy difference between the free-energy of the most stable state and that of the first metastable state. The energy difference is strongly related to the defect density in DSA process. As a result of our rigorous simulations, the process margin of the pinning layer width was found to be: (1) worse when the pinning layer affinity is too large, (2) better when the background affinity has the opposite sign of the pinning layer affinity, and (3) better when the top of the background layer is higher than that of the pinning layer by 0.1L0.

RIE challenges for sub-15 nm line-and-space patterning using directed self-assembly lithography with coordinated line epitaxy (COOL) process

Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the “coordinated line epitaxy (COOL) process,” using grapho- and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Electrical yield verification of half-pitch 15 nm patterns using directed self-assembly of polystyrene-block-poly(methyl methacrylate)

A novel half-pitch (HP) 15 nm line pattern multiplication process with simple process steps and low cost-of-ownership using a polystyrene-block-poly(methyl methacrylate) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrical yield verification of HP 15 nm metal wire circuits fabricated by the HP 15 nm line pattern multiplication process was carried out on a 300 mm wafer. The electrical yield verification revealed the viability of the HP 15 nm line pattern multiplication process from the perspective of the total practical performance including critical dimension control, defect control, local placement error, line width roughness, line edge roughness, and process windows in the pattern transfer process.

Novel fine-tuned model-based SRAF generation method using coherence map

We have developed the comprehensive sub-resolution assist features (SRAFs) generation method based upon the modulation of the coherence map. The method has broken through the trade-off relation between processing time and accuracy of the SRAF generation. We have applied this method to a real device layout and the average of Process Variation band width (PV band width) has improved to 40% without any processing time loss.

Control of morphological defects at the boundary between the periodic and non-periodic patterns in directed self-assembly process

In this study, we investigated a directed self-assembly (DSA) flow that could include a non-periodic pattern (i.e., wide line) lying in between the periodic line/space patterns, in a relatively simple and inexpensive way. A symmetric poly(styrene-block-methyl methacrylate) (PS-b-PMMA) with the natural periodicity (L0) of 30 nm was employed here. Our DSA flow has two key features. First, we used a hybrid approach that combined chemoepitaxy and graphoepitaxy methods to generate PMMA-attractive pinning guide patterns directly from ArF resist. Second, we attempted to utilize both the perpendicular lamellae in the periodic regions and the horizontal lamellae on the non-periodic pattern as an etch template. The advantage of this process will be a reduction of the number of lithographic processes, whereas the challenge is how to control the mixed morphologies at the boundary between the periodic and non-periodic regions. Our preliminary results from simulations and experiments showed that, in order to generate the horizontal lamellae on the non-periodic pattern, the PS-b-PMMA thickness on top of the non-periodic guide pattern should roughly match to ~1 L0, and the width of the non-periodic pattern should be larger than ~3-4 L0. In addition, the space between the periodic and non-periodic regions was found to be critical and it should be basically equal to the space between the guiding pins in the periodic regions (~75 nm) to minimize the formation of fingerprint morphology at the boundaries.

A simulation study on bridge defects in lamellae-forming diblock copolymers

In this paper we will describe a self-consistent field theory simulation study on bridge defects in lamellae-forming diblock copolymers. Because the bridge defects are buried three-dimensional defects formed in the diblock copolymer film, it is difficult to observe and determine what causes them. To determine the cause of the bridge defects effectively, self-consistent field theory simulations were used. By reproducing structural characteristics of the bridge defects in the simulation, the cause of the bridge defects were clarified. Finally, we discussed ways to prevent the bridge defects.