Yuriko Seino

Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Abstract. A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b-PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5  nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

Novel error mode analysis method for graphoepitaxial directed self-assembly lithography based on the dissipative particle dynamics method

Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full advantage of DSAL requires diminishing not only systematic error modes but also random error modes by carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only systematic errors but also random errors qualitatively by simulations.

Dissipative particle dynamics simulations to optimize contact hole shrink process using graphoepitaxial directed self-assembly

Dissipative particle dynamics (DPD) simulations are utilized to optimize contact hole shrink process using graphoepitaxial directed self-assembly (DSA). In this work, poly (styrene-block-methyl methacrylate) (PS-b-PMMA) was employed. In the contact hole shrink process, PS residual layer was formed on the bottom floor of the hole type prepattern. To realize reliable contact hole shrink process, minimization of the thickness of PS residual layer was one of the key issues. It was found that the minimization of the thickness of the PS residual layer and optimization of threedimensional configuration of the PMMA domain was trade-off relationship. By using DPD simulations, the parameters were successfully optimized to achieve residual layer free contact hole shrink of DSA lithography.

Contact hole shrink process using directed self-assembly

We report on a contact hole shrink process using directed self-assembly. A diblock copolymer, poly (styrene-blockmethyl methacrylate) (PS-b-PMMA), is used to shrink contact holes. Contact hole guide patterns for graphoepitaxy are formed by ArF photoresists. Cylindrical domains of PMMA is removed using organic solvents after DUV (λ <200 nm) irradiation. In this work, it is found that a solvent system is the best developer from the evaluated single solvent systems and mixed solvent systems. The wet development of PS-b-PMMA strongly depends on total exposure dose of DUV irradiation. With lower exposure dose, the cylindrical domains of PMMA are not clearly removed. With optimum exposure dose, PMMA is developed clearly. The contact hole guide patterns of 75 nm in diameter are successfully shrunk to 20 nm in diameter using the wet development process.

Sub-45nm resist process using stacked-mask process

The stacked-mask process (S-MAP) is a tri-level resist process by lithography and dry etching, which consists of thin resist, spin-on-glass (SOG), and spun-on carbon (SOC). However, as design rules progress below 60nm, two problems arise in the conventional S-MAP: 1) the deformation of SOC line pattern during SiO2 reactive ion etching (RIE), 2) the degradation of lithography performance due to high reflectivity at the interface between resist and SOG in high NA. In this study, we clarified the origin of the above problems and improved S-MAP materials and processes. Firstly, we found that the pattern deformation is induced by the inner stress due to volume expansion by fluorination during RIE, and that the deformation is suppressed by decreasing hydrogen content of SOC. Secondly, we developed new carbon-containing SOG that coexists with low reflectivity and acceptable etching performance. Using the above SOG and SOC, we developed a new S-MAP that shows an excellent lithography / etching performance in sub-45nm device fabrication.

Directed self-assembly lithography using coordinated line epitaxy (COOL) process

In this study, half-pitch (HP) 15 nm line-and-space (L/S) metal wires were successfully fabricated and fully integrated on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA, we developed a simple sub-15 nm L/S patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP), which utilizes trimming resist and shallow etching spin-on-glass (SOG) as pinning guide[1]-[4]. From the results of defect inspection after SOG etch using Electron Beam (EB) inspection system, defects were classified as typical DSA defects or defects relating to DSA pattern transfer. From the evaluation of DSA L/S pattern Critical Dimension (CD), roughness and local placement error using CD-SEM, it is considered that isolated PS lines are placed at the centerline between guides and that placement of paired PS lines depends on the guide width. The control of the guide resist CD is the key to local placement error and the paired lines adjacent to the guide shifted toward the outside (0.5 nm) along the centerline of the isolated line after SOG etch. We demonstrated fabrication of HP 15 nm metal wires in trenches formed by the DSA process with reactive ion etching (RIE), followed by metal chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). By SEM observation of alignment errors between the trenches and connect spaces, overlay shift patterns (-4 nm) in guide lithography mask were fabricated without intra-wafer alignment errors.

Perpendicular Orientation Control without Interfacial Treatment of RAFT-Synthesized High-χ Block Copolymer Thin Films with Sub-10 nm Features Prepared via Thermal Annealing

In this study, a series of perpendicular lamellae-forming poly(polyhedral oligomeric silsesquioxane methacrylate-block-2,2,2-trifluoroethyl methacrylate)s (PMAPOSS-b-PTFEMAs) was developed based on the bottom-up concept of creating a simple yet effective material by tailoring the chemical properties and molecular composition of the material. The use of silicon (Si)-containing hybrid high-χ block copolymers (BCPs) provides easy access to sub-10 nm feature sizes. However, as the surface free energies (SFEs) of Si-containing polymers are typically vastly lower than organic polymers, this tends to result in the selective segregation of the inorganic block onto the air interface and increased difficulty in controlling the BCP orientation in thin films. Therefore, by balancing the SFEs between the organic and inorganic blocks through the use of poly(2,2,2-trifluoroethyl methacrylate) (PTFEMA) on the organic block, a polymer with an SFE similar to Si-containing polymers, orientation control of the BCP domains in thin films becomes much simpler. Herein, perpendicularly oriented BCP thin films with a χeff value of 0.45 were fabricated using simple spin-coating and thermal annealing processes under ambient conditions. The thin films displayed a minimum domain size of L0 = 11 nm, as observed via atomic force microscopy (AFM), scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Furthermore, directed self-assembly (DSA) of the BCP on a topographically prepatterned substrate using the grapho-epitaxy method was used to successfully obtain perpendicularly oriented lamellae with a half pitch size of ca. 8 nm.

Defect-aware process margin for chemo-epitaxial directed self-assembly lithography using simulation method based on self-consistent field theory

We proposed a new concept of “defect-aware process margin.” Defect-aware process margin was evaluated by investigating the energy difference between the free-energy of the most stable state and that of the first metastable state. The energy difference is strongly related to the defect density in DSA process. As a result of our rigorous simulations, the process margin of the pinning layer width was found to be: (1) worse when the pinning layer affinity is too large, (2) better when the background affinity has the opposite sign of the pinning layer affinity, and (3) better when the top of the background layer is higher than that of the pinning layer by 0.1L0.

RIE challenges for sub-15 nm line-and-space patterning using directed self-assembly lithography with coordinated line epitaxy (COOL) process

Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the “coordinated line epitaxy (COOL) process,” using grapho- and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.

Electrical yield verification of half-pitch 15 nm patterns using directed self-assembly of polystyrene-block-poly(methyl methacrylate)

A novel half-pitch (HP) 15 nm line pattern multiplication process with simple process steps and low cost-of-ownership using a polystyrene-block-poly(methyl methacrylate) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrical yield verification of HP 15 nm metal wire circuits fabricated by the HP 15 nm line pattern multiplication process was carried out on a 300 mm wafer. The electrical yield verification revealed the viability of the HP 15 nm line pattern multiplication process from the perspective of the total practical performance including critical dimension control, defect control, local placement error, line width roughness, line edge roughness, and process windows in the pattern transfer process.